Allowing Shared Libraries While Supporting Hardware Isolation in Multicore Real-Time Systems

Kim, Nam Hoon; Chisholm, Micaiah; Otterness, Nathan; Anderson, James H.; Smith, F. Donelson

doi:10.1109/rtas.2017.14

Cited by 13 publications

(9 citation statements)

References 23 publications

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“…Additionally, applications still cross the boundaries of their colors when interacting with the OS itself. Finally, special care must be taken for applications that share dynamically linked libraries [14].…”

Section: A Coloring Strategy For Strict Partitioningmentioning

confidence: 99%

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Kloda

Solieri

Mancuso

et al. 2019

2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, highperformance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in highperformance embedded systems. Our approach leverages OStransparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks.

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Section: A Coloring Strategy For Strict Partitioningmentioning

confidence: 99%

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Kloda

Solieri

Mancuso

et al. 2019

2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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“…Researchers in [6,41,47,66] have developed coordinated allocation schemes for CPU and memory bandwidth resources, but they ignored the cache resource. Researchers in [30,31,55] considered the cache and memory bank resources but ignored the memory bandwidth resources. Researchers in [17] proposed a multi-resource allocation algorithm for real-time mixed criticality systems, which focuses on the tradeoffs of the cache allocation while considering the memory bank allocation.…”

Section: Related Workmentioning

confidence: 99%

Holistic Resource Allocation for Multicore Real-Time Systems

Phan

Choi

et al. 2019

2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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This paper presents CaM, a holistic cache and memory bandwidth resource allocation strategy for multicore real-time systems. CaM is designed for partitioned scheduling, where tasks are mapped onto cores, and the shared cache and memory bandwidth resources are partitioned among cores to reduce resource interferences due to concurrent accesses. Based on our extension of LITMUS RT with Intel's Cache Allocation Technology and MemGuard, we present an experimental evaluation of the relationship between the allocation of cache and memory bandwidth resources and a task's WCET. Our resource allocation strategy exploits this relationship to map tasks onto cores, and to compute the resource allocation for each core. By grouping tasks with similar characteristics (in terms of resource demands) to the same core, it enables tasks on each core to fully utilize the assigned resources. In addition, based on the tasks' execution time behaviors with respect to their assigned resources, we can determine a desirable allocation that maximizes schedulability under resource constraints. Extensive evaluations using real-world benchmarks show that CaM offers near optimal schedulability performance while being highly efficient, and that it substantially outperforms existing solutions.

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“…OS-supported IPC. Previous work on MC 2 speci cally focused on data sharing, but took a limited view of the solution: it only supported user-level IPC using shared memory [28]. is limitation facilitates maximizing isolation, because it avoids the need for system calls or dynamic memory allocations.…”

Section: Types Of Data Sharingmentioning

confidence: 99%

“…However, shared-memory IPC is insu cient in many cases. For example, even simple message-passing systems require in-memory synchronization primitives or wait-free data structures (as the authors of [28] recommend). ese shortcomings are addressed by other IPC mechanisms such as message queues or pipes, but these mechanisms break isolation because, in addition to sharing with other tasks, they require sharing data with the OS kernel.…”

Section: Types Of Data Sharingmentioning

confidence: 99%

“…us, when sharing is considered in the context of the one-out-of-m problem, the focus inevitably shi s to the weaker goal of lessening its impact. Prior work in this direction by our group has addressed user-level data sharing [10] and the usage of shared libraries [10,28] in the context of a hardware-isolation framework targeting mixed-criticality systems called MC 2 (mixed-criticality on multicore) [9-11, 17, 28, 30, 36, 48]. However, no work on the one-out-of-m problem has heretofore been published that investigates techniques for lessening the impact of OS-induced sharing by optimizing memory allocations.…”

Section: Introductionmentioning

confidence: 99%

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Supporting I/O and IPC via Fine-Grained OS Isolation for Mixed-Criticality Real-Time Tasks

Kim

Tang

Otterness

et al. 2018

Proceedings of the 26th International Conference on Real-Time Networks and Systems

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E orts towards hosting safety-critical, real-time applications on multicore platforms have been stymied by a problem dubbed the "one-out-of-m" problem: due to excessive analysis pessimism, the overall capacity of an m-core platform can easily be reduced to roughly just one core. e predominant approach for addressing this problem introduces hardware-isolation techniques that ameliorate contention experienced by tasks when accessing shared hardware components, such as DRAM memory or caches. Unfortunately, in work on such techniques, the operating system (OS), which is a key source of potential interference, has been largely ignored. Most real-time OSs do facilitate the use of a coarse-grained partitioning strategy to separate the OS from user-level tasks. However, such a strategy by itself fails to address any data sharing between the OS and tasks, such as when OS services are required for interprocess communication (IPC) or I/O. is paper presents techniques for lessening the impacts of such sharing, speci cally in the context of MC 2 , a hardware-isolation framework designed for mixed-criticality systems. Additionally, it presents the results from micro-benchmark experiments and a large-scale schedulability study conducted to evaluate the e cacy of the proposed techniques and to elucidate sharing vs. isolation tradeo s involving the OS. is is the rst paper to systematically consider such tradeo s and consequent impacts of OS-induced sharing on the one-out-of-m problem. CCS CONCEPTS •Computer systems organization → Multicore architectures; Embedded so ware; Real-time system architecture; •So ware and its engineering → Memory management; Embedded so ware; Realtime schedulability; Communications management;

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Allowing Shared Libraries While Supporting Hardware Isolation in Multicore Real-Time Systems

Cited by 13 publications

References 23 publications

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Holistic Resource Allocation for Multicore Real-Time Systems

Supporting I/O and IPC via Fine-Grained OS Isolation for Mixed-Criticality Real-Time Tasks

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