ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Klein, Joshua P.; Boybat, Irem; Qureshi, Yasir H.; Dazzi, Martino; Levisse, Alexandre; Ansaloni, Giovanni; Zapater, Marina; Sebastian, Abu; Atienza, David

doi:10.48550/arxiv.2205.10042

Cited by 3 publications

(3 citation statements)

References 37 publications

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“…Their solution employs a multiplicity of crossbars interfaced to content-addressable memories. A tightly-coupled solution for AIMC integration is introduced in ALPINE [8]. The authors of this paper focus on different applications with respect to us: multi-layer perceptrons, recurrent neural networks, and convolutional neural networks, where matrix-vector multiplications (as opposed to the GEMMs) are the main computational bottleneck.…”

Section: Related Workmentioning

confidence: 99%

TiC-SAT

Amirshahi

Klein

Ansaloni

et al. 2023

Proceedings of the 28th Asia and South Pacific Design Automation Conference

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Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constrained platforms. Furthermore, while loosely-coupled hardware accelerators have been proposed in the literature, data transfer costs limit their speed-up potential. We address this challenge along two axes. First, we introduce tightly-coupled, small-scale systolic arrays (TiC-SATs), governed by dedicated ISA extensions, as dedicated functional units to speed up execution. Then, thanks to the tightly-coupled architecture, we employ software optimizations to maximize data reuse, thus lowering miss rates across cache hierarchies. Full system simulations across various BERT and Vision-Transformer models are employed to validate our strategy, resulting in substantial application-wide speed-ups (e.g., up to 89.5X for BERT-large). TiC-SAT is available as an open-source framework 1 . CCS CONCEPTS• Computer systems organization → Neural networks; Systolic arrays; • Computing methodologies → Natural language processing; • Hardware → Hardware-software codesign.

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Section: Related Workmentioning

confidence: 99%

TiC-SAT

Amirshahi

Klein

Ansaloni

et al. 2023

Proceedings of the 28th Asia and South Pacific Design Automation Conference

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“…With the advent of deep networks for artificial intelligence [1], and the increasing need of special purpose low-power devices that can complement general-purpose power-hungry computers in 'edge computing' applications [2, 3], several types of event-based approaches for implementing spiking neural networks (SNNs) in dedicated hardware have been proposed [4][5][6][7][8][9]. While many of these approaches are focusing on supporting the simulation of large scale SNNs [4,6,9], on converting rate-based artificial neural networks (ANNs) into their spike-based equivalent networks [10][11][12], or on processing digitally stored data with digital hardware implementations [13][14][15][16][17], the original neuromorphic engineering approach, first introduced in the early '90 s, proposed to implement biologically plausible SNNs by exploiting the physics of subthreshold analog complementary metal-oxide-semiconductor (CMOS) circuits to directly emulate the bio-physics of biological neurons and synapses [18,19].…”

Section: Introductionmentioning

confidence: 99%

Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems

Zendrikov¹,

Solinas

Indiveri

2023

Neuromorph. Comput. Eng.

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Neuromorphic processing systems implementing spiking neural networks with mixed signal analog/digital electronic circuits and/or memristive devices represent a promising technology for edge computing applications that require low power, low latency, and that cannot connect to the cloud for oﬀ-line processing, either due to lack of connectivity or for privacy concerns. However, these circuits are typically noisy and imprecise, because they are aﬀected by device-to-device variability, and operate with extremely small currents. So achieving reliable computation and high accuracy following this approach is still an open challenge that has hampered progress on the one hand and limited widespread adoption of this technology on the other. By construction, these hardware processing systems have many constraints that are biologically plausible, such as heterogeneity and non-negativity of parameters. More and more evidence is showing that applying such constraints to artiﬁcial neural networks, including those used in artiﬁcial intelligence, promotes robustness in learning and improves their reliability. Here we delve even more in neuroscience and present network-level brain-inspired strategies that further improve reliability and robustness in these neuromorphic systems: we quantify, with chip measurements, to what extent population averaging is eﬀective in reducing variability in neural responses, we demonstrate experimentally how the neural coding strategies of cortical models allow silicon neurons to produce reliable signal representations, and show how to robustly implement essential computational primitives, such as selective ampliﬁcation, signal restoration, working memory, and relational networks, exploiting such strategies. We argue that these strategies can be instrumental for guiding the design of robust and reliable ultra-low power electronic neural processing systems implemented using noisy and imprecise computing substrates such as subthreshold neuromorphic circuits and emerging memory technologies.

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“…With the advent of deep networks for artificial intelligence [1], and the increasing need of special purpose low-power devices that can complement general-purpose power-hungry computers in “edge computing” applications [2, 3], several types of event-based approaches for implementing Spiking Neural Networks (SNNs) in dedicated hardware have been proposed [4–9]. While many of these approaches are focusing on supporting the simulation of large scale SNNs [4, 6, 9], on converting rate-based Artificial Neural Networks (ANNs) into their spike-based equivalent networks [10–12], or on processing digitally stored data with digital hardware implementations [13–17], the original neuromorphic engineering approach, first introduced in the early’90s, proposed to implement biologically plausible SNNs by exploiting the physics of subthreshold analog Complementary Metal-Oxide-Semiconductor (CMOS) circuits to directly emulate the bio-physics of biological neurons and synapses [18, 19].…”

Section: Introductionmentioning

confidence: 99%

Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems

Zendrikov

Solinas

Indiveri

2022

Preprint

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Neuromorphic processing systems implementing spiking neural networks with mixed signal analog/digital electronic circuits and/or memristive devices represent a promising technology for edge computing applications that require low power, low latency, and that cannot connect to the cloud for off-line processing, either due to lack of connectivity or for privacy concerns. However these circuits are typically noisy and imprecise, because they are affected by device to device variability, and operate with extremely small currents. So achieving reliable computation and high accuracy following this approach is still an open challenge that has hampered progress on one hand and limited widespread adoption of this technology on the other. By construction, these hardware processing systems have many constraints that are biologically plausible, such as heterogeneity and non-negativity of parameters. More and more evidence is showing that applying such constraints to artificial neural networks, including those used in artificial intelligence, promotes robustness in learning and improves their reliability. Here we delve even more in neuroscience and present network-level brain-inspired strategies that further improve reliability and robustness in these neuromorphic systems: we quantify, with chip measurements, to what extent population averaging is effective in reducing variability in neural responses, we demonstrate experimentally how the neural coding strategies of cortical models allow silicon neurons to produce reliable signal representations, and show how to robustly implement essential computational primitives, such as selective amplification, signal restoration, working memory, and relational networks, exploiting such strategies. We argue that these strategies can be instrumental for guiding the design of robust and reliable ultra-low power electronic neural processing systems implemented using noisy and imprecise computing substrates such as subthreshold neuromorphic circuits and emerging memory technologies.

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ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Cited by 3 publications

References 37 publications

TiC-SAT

TiC-SAT

Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems

Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems

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