Alternatives to aluminum gates for silicon quantum devices: Defects and strain

Abstract

Gate-defined quantum dots benefit from the use of small grain size metals for gate materials because they aid in shrinking the device dimensions. However, it is not clear what differences arise with respect to process-induced defect densities and inhomogeneous strain. Here, we present measurements of fixed charge, Qf; interface trap density, Dit; the intrinsic film stress, σ; and the coefficient of thermal expansion, α, as a function of forming gas anneal temperature for Al, Ti/Pd, and Ti/Pt gates. We show that Dit is minimized at an anneal temperature of 350 °C for all materials, but Ti/Pd and Ti/Pt have higher Qf and Dit compared to Al. In addition, σ and α increase with anneal temperature for all three metals with α larger than the bulk value. These results indicate that there is a trade-off between minimizing defects and minimizing the impact of strain in quantum device fabrication.

Electrical Control of Uniformity in Quantum Dot Devices

“…Yet, potential fluctuations are naturally present, as illustrated in Figure c. They can be caused by defects, charge traps and mechanical stress induced by the deposition of metallic gates, , as well as variations in material growth or in the exact shape of the gates. The development of devices based on quantum wells buried in heterostructures, similar to that sketched in Figure a, already has led to a drastic improvement of the uniformity compared to metal oxide semiconductor systems .…”

“…These traps could be bound states in the nonoxidized part of the silicon capping layer or at its SiGe interface. They can be induced by charge defects in the gate oxide or emerge due to mechanical stress originating from the deposition of metallic gates. , Also, charge trapping into and out of unpassivated silicon and germanium dangling bonds, − charge trapping in the oxide itself mediated by leakage currents, ,− or movement of mobile ions might be underlying the hysteresis. In all cases, when the gate voltage stress is removed, the charges would be expected to be immobile at the device operation temperature and would cause local shifts in the intrinsic potential landscape observable as alterations in the pinch-off characteristics.…”

Single-Electron Occupation in Quantum Dot Arrays at Selectable Plunger Gate Voltage

“…Substantial reductions in variability have been achieved through progress in heterostructure growth and device fabrication. For instance, these efforts focus on reducing material disorder, − advancing device fabrication, − and addressing fluctuations in mechanical stress induced by the deposition of metallic gate electrodes. − However, significant variations remain observable in current devices, ,, and it is an open question whether sufficient uniformity can be reached through material development alone.…”