Amelioration of interface state response using band engineering in III-V quantum well metal-oxide-semiconductor field-effect transistors

Yuan, Ze; Nainani, Aneesh; Bennett, B. R.; Boos, J.B.; Ancona, Mario G.; Saraswat, Krishna C.

doi:10.1063/1.3699226

Cited by 11 publications

(5 citation statements)

References 24 publications

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“…The results presented so far pertain to interfaces of bulk or bulk-like layers of semiconductors aiming at revealing behavior of the intrinsic DOS at the interfaces with insulating oxides. In recent years, however, a large number of semiconductor heterojunctions have been introduced at the interfaces with insulating oxides to facilitate better interface passivation [147,148], to introduce additional barrier layer The vertical lines mark the energy onsets of direct optical transitions between high symmetry points in the Brillouin zone of the Ge substrate crystal. The inset illustrates determination of the electron IPE threshold Φ (Ge/HfO 2 ) marked by the vertical line using 1/3 -ℎ] plots.…”

Section: Ipe From Semiconductor Heterojunctions and Band Offsetmentioning

confidence: 99%

Electron Band Alignment at Interfaces of Semiconductors with Insulating Oxides: An Internal Photoemission Study

Afanasʼev

2014

Advances in Condensed Matter Physics

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Evolution of the electron energy band alignment at interfaces between different semiconductors and wide-gap oxide insulators is examined using the internal photoemission spectroscopy, which is based on observations of optically-induced electron (or hole) transitions across the semiconductor/insulator barrier. Interfaces of various semiconductors ranging from the conventional silicon to the high-mobility Ge-based (Ge,Si1-xGex,Ge1-xSnx) andAIIIBVgroup (GaAs,InxGa1-xAs, InAs, GaP, InP, GaSb, InSb) materials were studied revealing several general trends in the evolution of band offsets. It is found that in the oxides of metals with cation radii larger than≈0.7 Å, the oxide valence band top remains nearly at the same energy (±0.2 eV) irrespective of the cation sort. Using this result, it becomes possible to predict the interface band alignment between oxides and semiconductors as well as between dissimilar insulating oxides on the basis of the oxide bandgap width which are also affected by crystallization. By contrast, oxides of light elements, for example, Be, Mg, Al, Si, and Sc exhibit significant shifts of the valence band top. General trends in band lineup variations caused by a change in the composition of semiconductor photoemission material are also revealed.

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Section: Ipe From Semiconductor Heterojunctions and Band Offsetmentioning

confidence: 99%

Electron Band Alignment at Interfaces of Semiconductors with Insulating Oxides: An Internal Photoemission Study

Afanasʼev

2014

Advances in Condensed Matter Physics

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“…In addition, the application of compressive strain into antimonide materials can be regarded as quite effective in boosting the hole mobility. 15,242) There have recently been many reports on GaSb, 178,182,202,[243][244][245][246][247][248] InGaSb, 168,170,247,[249][250][251][252] and InSb [253][254][255] p-MOSFETs. Some of them have exhibited fairly good hole effective mobility.…”

Section: Iii-v Cmosmentioning

confidence: 99%

III–V/Ge channel MOS device technologies in nano CMOS era

Takagi

Zhang

Suh

et al. 2015

Jpn. J. Appl. Phys.

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CMOS utilizing high-mobility III–V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III–V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III–V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III–V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III–V MOS device technologies, we mainly address the gate stack technology, III–V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III–V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III–V/Ge channels.

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“…Thus, much attention has been paid to GaSb-based p-MOSFETs, because of their higher hole mobility. As a result, there have recently been many reports on GaSb [37][38][39][40][41][42][43][44], InGaSb [40,[45][46][47] and InSb [48,49] p-MOSFETs. Some of them have exhibited fairly good hole effective mobility.…”

Section: Improvement Of Interface Defects At Gasb Mos Interfacementioning

confidence: 99%

(Invited) MOS Interface Control Technologies for Advanced III-V/ Ge Devices

et al. 2015

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Critical issues for high quality Ge/III-V MOS gate stacks have been reviewed and discussed. For Ge gate stacks, a plasma post oxidation method can realize high quality ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks. We have evaluated limiting factors of electron and hole mobility in Ge MOSFETs. The Ge MOS channel mobility in a high Ns region is significantly degraded by surface roughness scattering as well as trapping of free carriers into interface states inside the Ge bands. It is shown that reduction in surface roughness through low temperature PPO and reduction in Dit inside the bands due to atomic Deuterium annealing can improve the effective mobility in the high Ns region. For InGaAs gate stacks, ALD La2O3 gate stacks yield lower Dit than the Al2O3 ones. For GaSb gate stacks, high ALD temperature or annealing temperature increases Dit at Al2O3/GaSb interfaces. InAs passivation for GaSb surfaces can effectively significantly improve the MOS interface properties and the thermal stability of the Al2O3/GaSb interfaces.

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Amelioration of interface state response using band engineering in III-V quantum well metal-oxide-semiconductor field-effect transistors

Cited by 11 publications

References 24 publications

Electron Band Alignment at Interfaces of Semiconductors with Insulating Oxides: An Internal Photoemission Study

Electron Band Alignment at Interfaces of Semiconductors with Insulating Oxides: An Internal Photoemission Study

III–V/Ge channel MOS device technologies in nano CMOS era

(Invited) MOS Interface Control Technologies for Advanced III-V/ Ge Devices

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