AMLCD flicker model considering the V/sub T/ shift in a-Si:H TFT

Huang, Chung-Che; Constable, J.H.; Yost, Beth; Greene, Raymond G.

doi:10.1109/tdmr.2003.817676

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Drain bias stress-induced degradation in amorphous silicon thin film transistors with negative gate bias

Zhou

Wang

et al. 2011

18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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In this study, degradation of amorphous silicon thin film transistors (a-Si TFTs) under drain bias (V d ) stresses with fixed negative gate bias (V g ) has been investigated. For DC V d stress, state creation mechanism dominates the threshold voltage (V th ) degradation for relative large negative V gd (V g −V d ) while state creation and/or electron trapping dominates for positive V gd . For AC V d stress, state creation, electron trapping and hole trapping contribute to the degradation. Dominant mechanism depends on stress time, frequency and the polarity of V gd . Decreasing stress voltage suppresses state creation and/or hole trapping for −V gd condition, but enhances state creation and/or electron trapping for +V gd condition.

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