&amp;amp;amp;#x0394;-Encoding: Practical Encoded Processing

Kuvaiskii, Dmitrii; Fetzer, Christof

doi:10.1109/dsn.2015.20

Cited by 12 publications

(6 citation statements)

References 19 publications

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“…Functional simulator -Limited applicability -∼3× runtime overhead ANCode [11], ANBCode [37] Microprocessor datapath and memory NO ~10 6 instructions Functional simulator -∼10× runtime overhead Delta Encoding [20] Microprocessor datapath and memory NO ~10 3 instructions Functional simulator -∼5× runtime overhead…”

Section: Instructionsmentioning

confidence: 99%

“…Researchers have thoroughly investigated software-level data and computation encoding/decoding for hard and soft error protection [11,20,30,36,37]. The ED4I source-code transformation [30] generates a functionally equivalent AN-coded version of the program.…”

Section: Sotware Encoding/decodingmentioning

confidence: 99%

“…The schemes presented in [11,37] improve the eicacy of ED4I by utilizing more advanced coding mechanisms, for example, ANB and ANBD encoding, and addressing practical issues, that is, overlow through an intermediate-level compiler transformation. Unfortunately, such implementation of program encoding/decoding accompanies signiicant performance overhead (6× to more than 60× as reported in [37] and up to 250× reported in [20]). To overcome these limitations, [20] introduced delta-encoding, which is a source-to-source transformation that combines AN-encoding with instruction duplication.…”

Section: Sotware Encoding/decodingmentioning

confidence: 99%

“…Unfortunately, such implementation of program encoding/decoding accompanies signiicant performance overhead (6× to more than 60× as reported in [37] and up to 250× reported in [20]). To overcome these limitations, [20] introduced delta-encoding, which is a source-to-source transformation that combines AN-encoding with instruction duplication. However, software-only delta-encoding transformation still requires around 4.08 × execution time to achieve its maximum fault coverage, compared to unprotected architectures.…”

Section: Sotware Encoding/decodingmentioning

confidence: 99%

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EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults

Didehban

et al. 2022

ACM Trans. Archit. Code Optim.

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Error resilience is the primary design concern for safety- and mission-critical applications. Redundant MultiThreading (RMT) is one of the most promising soft and hard error resilience strategies because it does not require additional hardware modification. While the state-of-the-art software RMT scheme can achieve a high degree of error protection, our detailed investigation revealed that it suffers from performance overhead and insufficient fault coverage. This paper proposes EXPERTISE, a compiler-level RMT scheme that can detect the manifestation of hardware faults in all processor components. EXPERTISE transformation generates a checker-thread for the main execution thread. These redundant threads are executed simultaneously on two physically different cores of a multicore processor and perform almost the same computations. After each memory write operation is committed by the main-thread, the checker-thread loads back the written data from the memory and checks it against its own locally computed values. If they match, the execution continues. Otherwise, the error flag is raised. In order to evaluate the effectiveness of the proposed solution, we performed soft and hard error injection experiments on all the different hardware components of an ARM Cortex53-like μ -architecturally simulated microprocessor. Based on statistical fault injection campaigns, we have found that EXPERTISE provides 188 × better fault coverage with 27% faster performance as compared to the state-of-the-art scheme.

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Section: Instructionsmentioning

confidence: 99%

Section: Sotware Encoding/decodingmentioning

confidence: 99%

Section: Sotware Encoding/decodingmentioning

confidence: 99%

Section: Sotware Encoding/decodingmentioning

confidence: 99%

See 2 more Smart Citations

EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults

Didehban

et al. 2022

ACM Trans. Archit. Code Optim.

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“…In addition to the traditional approaches to ensure that the supervisor is correctly designed, we also need to ensure that it is correctly executed. Specifically, related work investigates the correct execution of the supervisor when executed on potentially unreliable hardware [25], under security attacks [28,5,27] or even protect its integrity despite the existence of CPU design faults [26].…”

Section: Related Workmentioning

confidence: 99%

Towards Dynamic Dependable Systems Through Evidence-Based Continuous Certification

Faqeh

Fetzer

Hermanns

et al. 2020

Leveraging Applications of Formal Methods, Verification and Validation: Engineering Principles

Self Cite

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Future cyber-physical systems are expected to be dynamic, evolving while already being deployed. Frequent updates of software components are likely to become the norm even for safety-critical systems. In this setting, a full re-certification before each software update might delay important updates that fix previous bugs, or security or safety issues. Here we propose a vision addressing this challenge, namely through the evidence-based continuous supervision and certification of software variants in the field. The idea is to run both old and new variants of component software inside the same system, together with a supervising instance that monitors their behavior. Updated variants are phased into operation after sufficient evidence for correct behavior has been collected. The variants are required to explicate their decisions in a logical language, enabling the supervisor to reason about these decisions and to identify inconsistencies. To resolve contradictory information, the supervisor can run a component analysis to identify potentially faulty components on the basis of previously observed behavior, and can trigger micro-experiments which plan and execute system behavior specifically aimed at reducing uncertainty. We spell out our overall vision, and provide a first formalization of the different components and their interplay. In order to provide efficient supervisor reasoning as well as automatic verification of supervisor properties we introduce SupERLog, a logic specifically designed to this end.

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Comprehensive Analysis of Software-Based Fault Tolerance with Arithmetic Coding for Performant Encoding of Integer Calculations

Fischer

Riedel²,

Lechler³

2022

Lecture Notes in Computer Science

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&amp;#x0394;-Encoding: Practical Encoded Processing

Cited by 12 publications

References 19 publications

EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults

EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults

Towards Dynamic Dependable Systems Through Evidence-Based Continuous Certification

Comprehensive Analysis of Software-Based Fault Tolerance with Arithmetic Coding for Performant Encoding of Integer Calculations

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