&amp;#x03B7;-&amp;#x03C1; Pareto optimization of 3-phase 3-level T-type AC-DC-AC converter comprising Si and SiC hybrid power stage

Uemura, Hirofumi; Krismer, Florian; Okuma, Yasuhiro; Kolar, Johann W.

doi:10.1109/ipec.2014.6870083

Cited by 22 publications

(4 citation statements)

References 15 publications

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“…Regarding the power loss, the loss characterisation of inductors in general, and their core loss in particular, has been a hot research topic. Accurate estimation of inductor core loss is crucial for the thermal design and optimisation of power converters [2]- [4] in early design stage. It is especially important when considers the high-frequency operation and associated highfrequency core loss with the use of wide-bandgap switching devices.…”

Section: Introductionmentioning

confidence: 99%

A Practical Approach for Core Loss Estimation of a High-Current Gapped Inductor in PWM Converters With a User-Friendly Loss Map

Wang

Dagan

Yuan

et al. 2019

IEEE Trans. Power Electron.

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Core loss estimation of filter inductors is critical for modelling and optimising high-frequency, highefficiency and high-density Pulse Width Modulation (PWM) power electronics converters. However, data provided by inductor core manufacturers is insufficient for core loss estimation in PWM converters, particularly in the case of customized gapped inductors. This paper presents a whole process of characterising and estimating the core loss of a customised high-current gapped inductor for PWM converters. To excite the inductor for the B-H loop measurement, a test circuit formed by a half-bridge structure is proposed, which has the ability to compensate the asymmetric rectangular voltage on the inductor caused by the device voltage drops. To overcome the other challenges raised by high excitation current, a discontinuous test procedure, Triple Pulse Test (TPT), is applied to reduce the requirements of the high-current test setup (thermal stress, current-time stress for current probes, capacity of dc sources, etc.). For practical purposes, a user-friendly loss map approach is proposed involving only time-domain and electrical variables to replace magnetic variables to enable straightforward loss mapping process and core loss calculations. Presented experimental results show consistency between the estimated inductor loss and measured values. Overall, the proposed testing approach can be easily implemented on the user's side to develop a loss map of a given inductor. The established core loss map enables the users to accurately and rapidly estimate the core loss of a tested inductor for given PWM waveforms.

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Section: Introductionmentioning

confidence: 99%

A Practical Approach for Core Loss Estimation of a High-Current Gapped Inductor in PWM Converters With a User-Friendly Loss Map

Wang

Dagan

Yuan

et al. 2019

IEEE Trans. Power Electron.

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“…It is shown that the configuration using RB-IGBTs shows lower total losses (conduction losses + switching losses) if compared with configurations using traditional IGBTs and, in high frequencies, the usage of simple Si IGBTs presented lower total losses. A η − ρ (efficiency-power density) Pareto front is developed in [181] for a Uninterruptible Power System (UPS) composed by the reduced switch count three-phase/level/wire T-Type rectifier (Fig. 29) sharing the same DC-link with a three-phase/level/wire T-Type inverter, using Si and SiC components.…”

Section: Discussionmentioning

confidence: 99%

A Survey on Multilevel Rectifiers With Reduced Switch Count

2023

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This paper presents a literature survey of more than twenty years on AC/DC multilevel converters with reduced switch count, in which some power switches can be removed letting only diodes. This simplification reduces the number of gate drivers, cost and complexity of the system. In this work, the considered topologies are derived from the conventional multilevel configurations on literature: Neutral Point Clamped, Cascaded H-Bridge, Flying Capacitor, Modular Multilevel Converter and T-Type. This article is divided in five sections, each one with papers with topologies derived from the five multilevel configurations previously mentioned. In each section, there are up to a maximum of four subsections, considering the main focus of each paper and contribution: derived and hybrid topologies, control techniques, analysis and hardware and design. At the end of each section, a summary table concerning the referenced papers is shown containing comparison information among the presented references in terms of: number of components per phase of the studied converter, applied modulation technique, applied control technique, suggested application given by the authors, converter's output power considered and the respective efficiency considering this point of operation. With this extensive bibliography work, this paper serves as a very good reference to researchers interested in the topic to initiate their work or to update their studies. Also, the applications suggested by the authors give a direction of which topologies fit best different applications.

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“…Using SiC power semiconductors, the maximum efficiency of the proposed converter is 99.0% and its efficiency at the rated power is 98.6%. In [25], an AC-AC multilevel converter based on T-Type topology with a peak efficiency of 96.6% and power density of 2.3 kW/dm 3 has been designed and tested for UPS applications. In [26], the three-phase AC-AC NPC converter has been proposed to supply the AC load starting from the grid.…”

Section: State Of the Artmentioning

confidence: 99%

Design of SiC-Si Hybrid Interleaved 3-Phase 5-Level E-Type Back-to-Back Converter

di Benedetto,

Lidozzi,

Grbović

2023

IEEE Open J. Power Electron.

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In modern applications, such as variable frequency electric drives, aircraft propulsion, electric vehicles, and uninterruptible power supply units, high power-dense, and efficient AC-AC power converters are the key to reducing power losses, thus limiting the overall costs, and improving the system's reliability. Power electronic equipment can be enhanced thanks to the continuous evolution of conversion topologies and advancements in power semiconductor technology. The design and the optimization strategy of the AC-AC 5-Level converter, called Interleaved 3-Phase 5-Level E-Type Back-to-Back Converter (I-3Φ5L BTB E-Type Converter), has been proposed in this paper. The converter is analyzed and experimentally characterized to prove the configuration's high efficiency and high-power density. An introduction to the characteristics of the I-3Φ5L BTB E-Type Converter is described, and afterward, the optimization methodology to design the multilevel converter is presented. The converter prototype is illustrated, which achieves a peak efficiency of 98.2% and a total weight of 6.18 kg using hybrid technology for power semiconductors..

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η-ρ Pareto optimization of 3-phase 3-level T-type AC-DC-AC converter comprising Si and SiC hybrid power stage

Cited by 22 publications

References 15 publications

A Practical Approach for Core Loss Estimation of a High-Current Gapped Inductor in PWM Converters With a User-Friendly Loss Map

A Practical Approach for Core Loss Estimation of a High-Current Gapped Inductor in PWM Converters With a User-Friendly Loss Map

A Survey on Multilevel Rectifiers With Reduced Switch Count

Design of SiC-Si Hybrid Interleaved 3-Phase 5-Level E-Type Back-to-Back Converter

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