AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits

Ayatollahi, Fateme Sadat; Ghaznavi‐Ghoushchi, M. B.; Mohammadzadeh, Naser; Ghamkhari, Seyedeh Fatemeh

doi:10.1109/tcsi.2021.3138139

Cited by 3 publications

(2 citation statements)

References 23 publications

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“…A variety of pipeline architecture has been proposed, considering their advantages and drawbacks. Recently, Ayatollahi et al revised few pipeline solutions to improve performance in digital circuits using 65 nm CMOS technology [11]. Pipeline scheduler automation is proposed to improve the speed performance from 1% to 128%, while reducing the register stages area from 20% to 74%.…”

Section: A Digital Synthesis Literaturementioning

confidence: 99%

Surface versus Performance Trade-offs: A Review of Layout Techniques

Ferreira

Avignon-Meseldzija

Bénabès

et al. 2022

JICS

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Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.

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Section: A Digital Synthesis Literaturementioning

confidence: 99%

Surface versus Performance Trade-offs: A Review of Layout Techniques

Ferreira

Avignon-Meseldzija

Bénabès

et al. 2022

JICS

View full text Add to dashboard Cite

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“…The demand for high-speed operation of electronic systems requires clock frequencies to be higher and timing specifications to be tighter [1]. For satisfying relevant timing requirements, high-speed circuits have been employed in these systems, which results in large power consumption.…”

Section: Introductionmentioning

confidence: 99%

Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging

Joo,

Kong

2023

IEEE Access

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Conventional high-performance flip-flops suffer from large power consumption at the nominal supply region and unreliable operation in the low-voltage region. To overcome these drawbacks, this paper proposes conditional-bridging flip-flops (CBFFs) that can conditionally activate the shorting device in the sense-amplifier stage. There are two versions of the proposed flip-flop. The single-ended version (CBFF-S) adopts a single-ended latching stage to optimize in terms of power consumption and area. For applications requiring high speed with differential outputs, the speed-optimized differential version (CBFF-D) is also proposed. Since the shorting device is adaptively turned on only when it is necessary, the flip-flops have fully static operations with reduced switching power consumption. The conditional bridging technique can also help minimize the effective parasitic capacitance relevant to the shorting device by relieving the design burden of weakening the device, resulting in further power reduction. The technique also provides the complete separation of complementary precharge nodes in the sense-amplifier stage during input sampling, achieving a fast and reliable operation. To further reduce power consumption and latency, the latching stage is designed to have no glitches and signal fighting, and to be driven by the output of the sense-amplifier stage without signal inversion. Moreover, the conditionally bridged sense-amplifier stage having a reliable pulldown of precharge nodes and the latching stage having a contention-free operation allow the flip-flops to provide stable operation down to the near-threshold voltage (NTV) region. The proposed flip-flops were designed in a 28-nm CMOS process, whose performance evaluation results indicated that the power consumption of CBFF-S is reduced by up to 56.2% compared to conventional single-ended flip-flops at 0.1 switching activity. The minimum DQ latency was also reduced by up to 33.6%. They also indicated that CBFF-D offers up to 33.8% less power at 0.1 switching activity, and up to 24.1% lower minimum DQ latency than those of conventional differential flip-flops. The resulting power-delay product (PDP) of CBFFs was at least 27.8% less than those of conventional flip-flops. The Monte-Carlo simulation results considering the process, voltage, and temperature (PVT) variations indicated that CBFFs could operate reliably down to a supply voltage of 0.3 V.INDEX TERMS Flip-flop, pulsed latch, sense amplifier, high performance, low power, low voltage

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Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2022

Wireless Pers Commun

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Multiplication is one of the basic functions in Digital Signal Processing (DSP) applications. Multiplier plays an important role in Arithmetic and Logic Unit (ALU), which is a critical element in the processors. The e ciency of the multiplier takes part a crucial task in the execution of the processor. The performance of the multiplier depends on the adder circuit. The addition operation is the fundamental operation used in most of the digital circuits. Power, delay and area are the main issues in VLSI circuits. E ciency of a VLSI circuit can be improved by rectifying any of these issues. Quaternary Signed Digits (QSD) placed on adders have better e ciency when compared to traditional binary logic. QSD based Carry Look Ahead (CLA) Adder is used to increase the e ciency with reference to power and delay. The proposed method uses Quaternary Carry Increment Adder in order to improve the power and reduce the delay of the existing Quaternary Carry Look Ahead Adder. Tanner EDA is the simulation tool used to design the circuits and the power, delay and power-delay product of the designed circuits are measured using it.

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AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits

Cited by 3 publications

References 23 publications

Surface versus Performance Trade-offs: A Review of Layout Techniques

Surface versus Performance Trade-offs: A Review of Layout Techniques

Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

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