An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

Abstract

This paper presents a pipeline analog to digital converter (ADC) consisting of five stages with 2.5 effective bit resolution. Several techniques were combined for the reduction of the power consumption and to preserve the converter linearity. To reduce the power consumption, the circuit has two scaled operational transconductance amplifiers (OTAs), which are shared by the first four pipeline stages. The last fifth stage is a single decoder with 2.5 effective bits. Each OTA includes additional circuitry to adapt the power consumption according to the stage that uses the OTA. This technique changes the bias current depending on the stage in operation. The ADC was optimized to obtain 11-bit resolution with frequencies from 1 kHz to 10 MHz. The technology used to simulate the ADC is a 3.3 V 0.35 µm CMOS process and the circuit consumes 17.9 mW at 20 MSample/s sampling rate. With this resolution and sampling rate, it achieves 67.28 dB SNDR and 10.88 bit ENOB at 0.1 MHz input frequency. The Figure of Merit is 0.473 pJ/step.

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

“…The structure of the four input OTA is shown in Fig. 3 [11]. Due to the requirements of the ADC, a telescopic OTA with gain boosting [16] has been used.…”

“…According to these values, the real values of the biasing current IBias (estimated and actual) and total current I T otal are those shown in Table 1. Different simulations [11] and measurements have been performed to evaluate the circuit performance. Fig.…”

“…The advantage of this approach is that it reduces the number of operational amplifiers compared to [17] while performing the same functionality of bias regulation. The circuit has been prototyped and tested following the biasing technique described in [11]. The main novelty is the implementation of the adaptive bias current and sharing OTA techniques at the same time.…”

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

“…So, a circuit varying the bias current of an amplifier, depending on the stage, contributes to cut down on power dissipation. An example of this technique applied to a 5-stage pipeline ADC is described in [17]. Finally, in [18] a reconfigurable pipeline converter employing parallel OTAs to reach optimal power dissipation over a wide sampling rate range is proposed.…”