2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2016
DOI: 10.1109/edssc.2016.7785288
|View full text |Cite
|
Sign up to set email alerts
|

An 11b 40MS/s charge pump and comparator based pipelined ADC with variable reset voltages

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1

Citation Types

0
12
0

Year Published

2021
2021
2021
2021

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(12 citation statements)
references
References 8 publications
0
12
0
Order By: Relevance
“…The conventional CCP circuit is depicted in Figure 4 4 . As the opamp is a power‐hungry block, the OTA in opamp‐based structure is replaced with a main detection comparator (SC) and a CCS in a typical CCP structure in order to reduce the power consumption of each stage.…”
Section: Ccp Structurementioning
confidence: 99%
See 4 more Smart Citations
“…The conventional CCP circuit is depicted in Figure 4 4 . As the opamp is a power‐hungry block, the OTA in opamp‐based structure is replaced with a main detection comparator (SC) and a CCS in a typical CCP structure in order to reduce the power consumption of each stage.…”
Section: Ccp Structurementioning
confidence: 99%
“…Amplifying the residue voltage with low power consumption is the main challenge in pipelined ADCs. Residue amplification in every stage can increase the accuracy by amplifying the signal into the full‐scale range 4,10 . Generating V RES is done by multiplying digital‐to‐analog converter (MDAC) block.…”
Section: Introductionmentioning
confidence: 99%
See 3 more Smart Citations