An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range

Bannon, Alan; Hurrell, Christopher Peter; Hummerston, Derek; Lyden, C.

doi:10.1109/vlsic.2014.6858371

Cited by 51 publications

(10 citation statements)

References 3 publications

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“…To avoid fractional bridge capacitors and facilitate the layout of CDAC, grounding capacitors, C GND2 and C GND3 are used in CDAC-2 and CDAC-3. The ideal grounding capacitor for CDAC-2, C GND2 and CDAC-3, C GND3 can be obtained with (20) and (21). They suggest C GND3 and C GND2 equivalent to 18.5 unitcapacitors and 9.0625 unit-capacitors, respectively.…”

Section: Cdac Schemementioning

confidence: 99%

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16‐bit 1‐MS/s SAR ADC with foreground digital‐domain calibration

Guan

Xue

Yang

et al. 2018

IET Circuits, Devices & Systems

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This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and 'segment error' of split-CDAC array is proposed. The split-CDAC architecture combines a V cm-free technique in a floating CDAC scheme. The V cm-free technique avoids a power hungry V cm generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 µm 1P6M Complementary Metal Oxide Semiconductor (CMOS) technology, and achieves 86.16 dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41 pJ/conversion-step.

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Section: Cdac Schemementioning

confidence: 99%

“…To obtain the weight estimation, the work in [10, 20] directly uses lower bit capacitors to estimate the weight of higher bit capacitors. For example, in [10], CDAC is non‐binary, as shown in Fig.…”

Section: Sar Adc Architecture and Foreground Digital‐domain Calibrationmentioning

confidence: 99%

16‐bit 1‐MS/s SAR ADC with foreground digital‐domain calibration

Guan

Xue

Yang

et al. 2018

IET Circuits, Devices & Systems

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“…The secondary bit has a weight equal to the redundancy of decision bit. The position of Secondary bit is written as Where k is denoted as distance between the decision and secondary bits and Wj is the weight of the decision bit [10]. b) Latched Comparator In a latched comparator, apart from thermal noise, clock feedthrough ,comparator offset voltage, kickback noise; and charge injection are also the main sources of errors.…”

Section: Proposed Architectural Implementation Of Sar-adcmentioning

confidence: 99%

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Dastagiri¹,

Kishore²

2018

IJET

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This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to-Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non-binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv.Step which is comparable with existing ADC topologies.

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“…The instantaneous drain source voltage of is reduced by , which is likely to be larger than the headroom of , driving into the triode region and deteriorating the slew rate. The instantaneous drain current of during the transient is given by (16) where is the current factor of . The of OTA has to increase in order to compensate for the slew rate degradation.…”

Section: Slew Rate Improvement Via Cascode Bias Switchingmentioning

confidence: 99%

“…Low small-signal bandwidth is desirable for low noise at the sampling instant, but that presents a challenge for achieving the desired settling accuracy. The proposed THA divides the amplification phase into two consecutive sub-phases with different bandwidths [16]. During the first sub-phase, it operates with high bandwidth to approach the final value quickly.…”

Section: Introductionmentioning

confidence: 99%

Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

Zhu

Kapusta

Kim

2015

IEEE Trans. Circuits Syst. I

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The conventional switched-capacitor amplifier faces design tradeoffs between settling accuracy and noise, in that high settling accuracy demands wide bandwidth but at the sacrifice of noise performance. In fact settling accuracy and noise exhibit different time dependence, which can be exploited to optimize the overall performance. Settling accuracy is determined by average bandwidth in the whole amplification phase, whereas the output noise of interest is determined by the bandwidth near the end of the phase. The proposed amplifier divides the amplification phase into two sub-phases. The first sub-phase starts with high bandwidth and high slew rate to approach the final value quickly. In the second sub-phase, the bandwidth can be significantly reduced, achieving the target settling accuracy but with much lower noise. This division allows the settling accuracy, noise, slew rate, and DC gain to be designed independently. A test chip is fabricated in a 65 nm CMOS process and operates at 90 MS/s. Measurements demonstrate that the proposed amplifier achieves 45% noise power reduction in the amplification phase along with improved linearity and lower power consumption, when compared with the conventional amplifier.Index Terms-Bandwidth, noise, slew rate, switched-capacitor, track-and-hold.

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An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range

Cited by 51 publications

References 3 publications

16‐bit 1‐MS/s SAR ADC with foreground digital‐domain calibration

16‐bit 1‐MS/s SAR ADC with foreground digital‐domain calibration

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

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