An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

Makino, Hiroshi; Nakase, Y.; Suzuki, Hiroyoshi; Morinaka, H.; Shinohara, Hirofumi; Mashiko, Kunihiro

doi:10.1109/4.509863

Cited by 113 publications

(77 citation statements)

References 13 publications

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“…Many RBA designs have been developed, and constant refinements are being tried out to improve the performance. The fastest redundant binary adder cell is described in [3], which also presents a small survey of previous work on RBA cell designs. The compactness of the proposed signeddigit adder design compares very well against Makino's RBA cell that requires about 56 MOS transistors [3], as opposed to only 19 devices used in this paper.…”

Section: Discussionmentioning

confidence: 99%

“…In signeddigit adders, it is possible to perform addition of two arbitrary size numbers in constant time, and redundant algorithms can, therefore, help to significantly improve the performance of arithmetic circuits in applications with large operand sizes. Signed-digit systems have been adopted by many researchers and designers in the development of high-performance arithmetic circuits [2], [3], [4], [5], but compact and efficient implementation of the signed-digit adders still remains somewhat elusive with the conventional device technologies.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed circuit is built compactly using only 13 MOS transistors and one two-peak RTD, in comparison to 56 transistors required by Makino et al's well-known CMOS redundant binary adder [3], and to 34 devices required by an efficient multivalued current-mode MOS adder proposed by Kawahito et al [20]. The signeddigit adder in this paper implements a radix-2 arithmetic system that uses ternary digit set {-1, 0, +1}.…”

Section: Introductionmentioning

confidence: 99%

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Multiple-valued signed digit adder using negative differential resistance devices

Gonzalez

Mazumder

1998

IEEE Trans. Comput.

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Abstract-This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple-valued logic literal circuit that utilizes the folded-back I-V (also known as negative differential-resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current-mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and, therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy-based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state-of-the-art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current-mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs-based RTDs connected externally to the MOSFET circuit.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Multiple-valued signed digit adder using negative differential resistance devices

Gonzalez

Mazumder

1998

IEEE Trans. Comput.

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“…An 8.8 ns 54;54-bit multiplier using redundant binary architecture Makino et al presented important work on redundant binary arithmetic in [13,22]. Makino's multiplier became the fastest multiplier of the time with an 8.8 ns multiply delay.…”

Section: 3mentioning

confidence: 99%

Redundant arithmetic, algorithms and implementations

Gonzalez

Mazumder

2000

Integration

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“…However, the synthesis of this implementation results in a very poor utilization for the FPGA logic elements. Alternatively, the adder can be implemented using logic gates based upon equations presented by [14].…”

Section: A Digit Set and Encodingmentioning

confidence: 99%

Fir Filter Design Using The Signed-Digit Number System and Carry Save Adders – A Comparison

Altwaijry¹,

Seddiq²

2013

IJACSA

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Abstract-This work looks at optimizing finite impulse response (FIR) filters from an arithmetic perspective. Since the main two arithmetic operations in the convolution equations are addition and multiplication, they are the targets of the optimization. Therefore, considering carry-propagate-free addition techniques should enhance the addition operation of the filter. The signed-digit number system is utilized to speedup addition in the filter. An alternative carry propagate free fast adder, carry-save adder, is also used here to compare its performance to the signed-digit adder. For multiplication, Booth encoding is used to reduce the number of partial products. The two filters are modeled in VHDL, synthesized and place-androuted. The filters are deployed on a development board to filter digital images. The resultant hardware is analyzed for speed and logic utilization

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An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

Cited by 113 publications

References 13 publications

Multiple-valued signed digit adder using negative differential resistance devices

Multiple-valued signed digit adder using negative differential resistance devices

Redundant arithmetic, algorithms and implementations

Fir Filter Design Using The Signed-Digit Number System and Carry Save Adders – A Comparison

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