An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

Oh, Dong-Ryeol; Moon, Kyong Whan; Lim, Won-Mook; Kim, Ye-Dam; An, Eun-Ji; Ryu, Seung‐Tak

doi:10.1109/jssc.2020.3044624

Cited by 20 publications

(6 citation statements)

References 22 publications

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“…The figure of merit (FoM) [68] of the proposed ADC is calculated from the Nyquist rate as 31.4 fJ/conversion step, which is better than that presented in prior work. Although [69,70] shows better FoM than this work, the power consumption is very high. While [40,63,68,71] exhibited a lower power consumption compared to this work, they have a higher DNL and INL, which degrades the linearity performance of the ADC.…”

Section: Adc Characterizationmentioning

confidence: 62%

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Biswas

Mahbub

2021

Electronics

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This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

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Section: Adc Characterizationmentioning

confidence: 62%

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Biswas

Mahbub

2021

Electronics

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“…The proposed ADC is similar to an asynchronous SAR ADC [6,7,8,9,10,11,12], a pipelined ADC [1], a subranging ADC [1], or a binary-search ADC [28,29,30,31] in some aspects, but has several different points.…”

Section: Discussionmentioning

confidence: 99%

“…The ADC is a key circuit for interface between analog and digital worlds [1,2,3]. Much attention has been paid to the SAR ADC due to small chip area and low power as well as no need for operational amplifier [4,5,6,7,8,9,10,11,12,13,14,15,16,17,18], and its figure of merits (FOM) has been improved. The Hopfield network has been investigated as an ADC architecture for several tens of years [19,20,21,22,23,24], but it has not been widely used in practice.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous capacitive SAR ADC based on Hopfield network

Bai

Katayama

Yao

et al. 2022

IEICE Electron. Express

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This letter revisits a Hopfield network for an SAR ADC configuration, which enables low voltage, low power and fast operation with small circuitry. It employs an asymmetrical Hopfield network to avoid local minimum, and it uses capacitors and switches instead of very large resistors. Our N-bit SAR ADC uses N chopper-type comparators with asynchronous parallel operation, which is different from the conventional asynchronous SAR ADC employing only one comparator. It requires only the sampling clock for each input data sampling; no internal high frequency clock is required. Its AD conversion time is determined only by the comparator delays and the capacitor charge/discharge settling times; hence it is very fast and the AD conversion latency is only one or two clock cycles. Its operation is verified with SPICE simulations.

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“…Nonetheless, SAR ADCs are slow to convert because they process 1 bit per cycle. To address the distinct limitations of both ADC types, a hybrid structure termed flash-SAR ADC (FS ADC) has been proposed [28,29]. By combining the advantages of flash ADC and SAR ADC, FS ADC can output digital values in half the clock cycle compared with conventional SAR ADCs, alleviating the slow conversion speed of SAR ADCs.…”

Section: Introductionmentioning

confidence: 99%

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

Lee,

Kim

2024

Electronics

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This study presents a charge-domain SRAM-based in-memory computing (IMC) architecture. The multiply-and-accumulate (MAC) operation in the IMC structure is divided into current- and charge-domain methods. Current-domain IMC has high-power consumption and poor linearity. Charge-domain IMC has reduced variability compared with current-domain IMCs, achieving higher linearity and enabling energy-efficient operation with fewer dynamic current paths. The proposed IMC structure uses a 9T1C bitcell considering the trade-off between the bitcell area and the threshold voltage drop by an NMOS access transistor. We propose an energy-efficient summation mechanism for 4-bit weight rows to perform energy-efficient MAC operations. The generated MAC value is finally returned as a digital value through an analog-to-digital converter (ADC), whose performance is one of the critical components in the overall system. The proposed flash-successive approximation register (SAR) ADC is designed by combining the advantages of flash ADC and SAR ADC and outputs digital values at approximately half the cycle of SAR ADC. The proposed charge-domain IMC is designed and simulated in a 65 nm CMOS process. It achieves 102.4 GOPS throughput and 33.6 TOPS/W energy efficiency at array size of 1 Kb.

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An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

Cited by 20 publications

References 22 publications

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Asynchronous capacitive SAR ADC based on Hopfield network

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

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