An 8-bit 166nw 11.25 kS/s 0.18um two-Step-SAR ADC for RFID applications using novel DAC architecture

Abstract

SAR ADCs have been mostly used for moderatespeed, moderate-resolution applications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC. In this paper an ultra low power two-step-SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with no static current and a dual-stage (Resistorstring / capacitive dividing) architecture as digital-to-analog converter (DAC). In this DAC architecture fine search will be performed by only two C and 15C capacitors which reduced the silicon area significantly. The circuit designed in 0.18um CMOS technology and simulations show that the 8-bit ADC, consumes almost 166nW at 11.25kS/s. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison with its charge redistribution counterpart.

An ultra low die area 8-b ADC and its generic calibration logic

“…that were published in the last 3 years and have similar resolution and known power, area and SINAD. It is obvious that the actual required area of the developed ADC is at least an order of magnitude lower than any other ADC except [8,9] that are based on successive approximation architecture. ADCs based on successive approximation require ultra low die area but are inherently targeted for low speed applications.…”

“…24 is multiplied by the V dd to favor low supply voltage implementations. A alternative figure of merit that takes into consideration the area and the dynamic resolution of an ADC is used in [8]. In Table 2, the standard FOM was estimated by expressing the power in mW and using a Nyquist sampling frequency expressed in MHz as F s .…”

“…On the contrary, applications like capacitance sensors and biosensor readout circuits, high fidelity sound processing systems etc., operate on input signals with frequencies of up to a few kHz but require ADCs of high accuracy in terms of static linearity and dynamic resolution [4][5][6][7][8][9]. A resolution higher than 8-bits is usually required in this case.…”

A Review Paper on A 10 Bit, Low Power ADC Suitable for Wireless Application

“…Usage of RFID is growing intensively in these days, as you can see it in supermarkets for cashless payment, warehousing, asset management and also airport baggage control, library management, medical monitoring and access/security control. So in this paper [2], SAR ADCs have been mostly used for moderatespeed, moderate-resolution pplications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC.…”

“…Unfortunately, in deep-submicron CMOS, the achievable gain per stage is limited because short-channel effects lower g m r 0 for a single transistor, and reduced voltage supplies restrict circuit techniques such as cascoding. Thus, there are significant challenges for continued scaling of pipelined ADCs [2]. Thus.…”