An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine

Correll, Justin M.; Lu, Jie; Song, Seungheun; Lee, Seungjong; Zhu, Junkang; Tang, Wei; Wormald, Luke; Erhardt, Jack; Breil, N.; Quon, Roger; Kamalanathan, Deepak; Krishnan, Siddarth; Chudzik, M.; Zhang, Zhengya; Lü, Wei; Flynn, Michael P.

doi:10.1109/vlsitechnologyandcir46769.2022.9830490

Cited by 27 publications

(3 citation statements)

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“…Our preliminary work in [98] indicates the latter to be the case for resistive crossbars because the input DAC mismatch and the input signal have the same transfer-function. This finding is supported by recent crossbar IMCs [61], [70] that allocate 80% of the bank area to the sensing circuitry/peripherals.…”

Section: A Energy Efficiency Vs Compute Densitysupporting

confidence: 53%

Benchmarking In-Memory Computing Architectures

Shanbhag

Roy

2022

IEEE Open J. Solid-State Circuits Soc.

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In-memory computing (IMC) architectures have emerged as a compelling platform to implement energy efficient machine learning (ML) systems. However, today, the energy efficiency gains provided by IMC designs seem to be leveling off and it is not clear what the limiting factors are. The conceptual complexity of IMCs combined with the absence of a rigorous benchmarking methodology makes it difficult to gauge progress and identify bottlenecks in this exciting field. This paper presents a benchmarking methodology for IMCs comprising: 1) a compositional view of IMCs that enables one to parse an IMC design into its canonical components; 2) a set of benchmarking metrics to quantify the performance, efficiency, and accuracy of IMCs; and 3) a strategy for analyzing the reported IMC data and metrics. We apply the proposed benchmarking methodology on an extensive database of IMC metrics extracted from > 70 IC designs published since 2018, in order to infer and comprehend trends in this area.Our benchmarking effort indicates: 1) SRAM-based IMCs show a clear win in terms of energy efficiency and compute density over digital accelerators at the bank-level but the energy efficiency gap reduces dramatically when comparing at the processor level; 2) eNVM-based IMCs lag behind SRAM-based IMCs in terms of both energy efficiency and compute density, and surprisingly lag digital accelerators in terms of compute density; 3) the compute (bank-level) accuracy of IMCs, though a critical metric, is pervasively neglected in publications as is the energy vs. accuracy trade-off inherent to IMCs.

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Section: A Energy Efficiency Vs Compute Densitysupporting

confidence: 53%

Benchmarking In-Memory Computing Architectures

Shanbhag

Roy

2022

IEEE Open J. Solid-State Circuits Soc.

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“…After the performance data is collected, the top-ranked sub-networks need to be searched, which requires ranking. In addition to the necessary array and drive circuits, the RMU also includes the sense amplifier (SA, used to read the state stored in the device), the row and column processor (used to select specified rows and columns and complete rank operations), the read and write (R&W) controller [42] (used to control read and write operations of devices in the array), the ranking controller (used to control and execute in-memory rank), as well as the mutation unit (used to adopt the superior sub-network structure found and distribute them to each core). The RMU will receive the evaluation results from each core, and the evaluation results will be written The evaluation results will be sent to RMU through topology evaluating unit (TEU).…”

Section: In-memory Mac and In-memory Rank With Pcmmentioning

confidence: 99%

Neural Architecture Search with In‐Memory Multiply–Accumulate and In‐Memory Rank Based on Coating Layer Optimized C‐Doped Ge₂Sb₂Te₅ Phase Change Memory

Yan

et al. 2023

Adv Funct Materials

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Neural architecture search (NAS), as a subfield of automated machine learning, can design neural network models with better performance than manual design. However, the energy and time consumptions of conventional software‐based NAS are huge, hindering its development and applications. Herein, 4 Mb phase change memory (PCM) chips are first fabricated that enable two key in‐memory computing operations—in‐memory multiply‐accumulate (MAC) and in‐memory rank for efficient NAS. The impacts of the coating layer material are systematically analyzed for the blade‐type heating electrode on the device uniformity and in turn NAS performance. The random weights in the searched network architecture can be fine‐tuned in the last stage. With 512 × 512 arrays based on 40 nm CMOS process, the PCM‐based NAS has achieved 25–53× smaller model size and better performance than manually designed networks and improved the energy and time efficiency by 4779× and 123×, respectively, compared with NAS running on graphic processing unit (GPU). This work can expand the hardware accelerated in‐memory operators, and significantly extend the applications of in‐memory computing enabled by nonvolatile memory in advanced machine learning tasks.

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“…I N-memory computing (IMC) is a widely recognized approach that aims to reduce the energy and latency costs associated with conventional von Neumann computing by performing computations directly within the memory array. A promising direction in IMC is the development of resistive IMCs [1]- [23] based on embedded non-volatile memory (eNVM) technologies, which leverage their non-volatility and high storage density properties.…”

Section: Introductionmentioning

confidence: 99%

Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures

Roy,

Shanbhag

2024

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This paper proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters that affect it. We further analyze the fundamental limits on the SNDR of MRAM, ReRAM, and FeFET-based IMCs employing parameter variation and noise models that were validated against measured results from a recent MRAMbased IMC prototype in a 22 nm process. At high output signal magnitude, we find that the maximum achievable SNDR is limited by the pre-ADC array non-idealities such as the conductance variations, parasitic resistances, and current mirror mismatch, whereas the ADC thermal noise limits the SNDR at small signal magnitudes. Furthermore, for large dot-product (DP) dimensions (N > 50), the maximum achievable SNDR is highest for FeFET, followed by ReRAM, and then MRAM. Finally, the increase in conductance contrast (g on /g off ) enhances the maximum achievable SNDR only until it reaches a value of approximately 12. ReRAMs and FeFETs demonstrate high energy efficiencies while achieving high SNDR, as their low conductance values lead to lower currents and lower noise due to wire parasitics. In all cases, across all three device types, DP dimension, ADC precision, and conductance contrast, the maximum achievable SNDR is found to be in the range of 18 dB-to-22 dB, barely meeting the minimum needed for achieving an inference accuracy close to an equivalent fixed-point digital architecture. Finally, we demonstrate a network-level accuracy of 84.5 % when mapping a ResNet-20 (CIFAR-10) by ReRAMbased architecture at a SNDR of 22 dB, which MRAM and FeFET-based architectures cannot realize. This result clearly implies the need for other approaches, e.g., algorithmic and learning-based methods, to improve the inference accuracy of resistive IMC architectures.

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An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine

Cited by 27 publications

References 0 publications

Benchmarking In-Memory Computing Architectures

Benchmarking In-Memory Computing Architectures

Neural Architecture Search with In‐Memory Multiply–Accumulate and In‐Memory Rank Based on Coating Layer Optimized C‐Doped Ge₂Sb₂Te₅ Phase Change Memory

Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures

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An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine

Cited by 27 publications

References 0 publications

Benchmarking In-Memory Computing Architectures

Benchmarking In-Memory Computing Architectures

Neural Architecture Search with In‐Memory Multiply–Accumulate and In‐Memory Rank Based on Coating Layer Optimized C‐Doped Ge2Sb2Te5 Phase Change Memory

Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures

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Neural Architecture Search with In‐Memory Multiply–Accumulate and In‐Memory Rank Based on Coating Layer Optimized C‐Doped Ge₂Sb₂Te₅ Phase Change Memory