An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications

Balakrishnan, Mani; Brox, M.; Chetreanu, Cristian; Dietrich, Stefan; Funfrock, Fabien; Gonzalez, Marcos Alvarez; Hein, Thomas; Huber, Eugen; Lauber, Daniel; Ivanov, Milena; Kuzmenka, Maksim; Mohr, Christian N.; Garrido, Juan Ocon; Padaraju, Swetha; Piatkowski, Sven; Pottgiesser, Jan; Pfefferl, Peter; Plan, Manfred; Polney, Jens; Rau, Stephan; Richter, Michael; Schneider, Ronny; Seitter, Ralf Oliver; Spirkl, W.; Walter, Marc D.; Weller, Jörg; Vitale, Filippo

doi:10.1109/jssc.2017.2737945

Cited by 13 publications

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“…The use of rising and falling edge of a multi-phase clock signal can be one of the solutions [1]. To increase per-pin data rate for graphics applications including game consoles, the state-of-the-art graphic DRAMs adopt quadrature data rate (QDR) interface [2,3,4]. In these QDR interface-based DRAMs, the multi-phase clocks with a low duty-cycle error and phase-skew is required for the improvement of the timing margin. However, while the duty cycle correction methods [5,6,7,8] have been extensively reported, an integrated structure that performs both duty-cycle correction and phase-skew correction in the QDR interface circuit has not been reported substantially.…”

Section: Introductionmentioning

confidence: 99%

An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs

Cho¹,

Min²

2018

IEICE Electron. Express

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Abstract:A compact all-digital duty-cycle and phase-skew correction circuit for quadrature data rate interface-based DRAM applications is presented. To improve the correction time, this work adopts a successive approximation register controller for both duty-cycle and phase-skew correction. The proposed correction circuit has been fabricated in a 65nm CMOS technology with a die area of 0.086mm [7] Y.-J. Min, et al.: "A 0.31-1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications," IEEE Trans.

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