An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers

This paper describes how the signal path within a ΔΣ modulator can be designed, independent of its noise-shaping characteristics, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to lower the power dissipation. This paper then presents architectural approaches for designing highresolution ΔΣ modulators at low oversampling ratios (OSRs) and low supply voltages. Thus, analog-to-digital converters (ADCs) can be designed in low-voltage nano-scale digital CMOS technologies to achieve high-speed and high-resolution A/D conversion, with high power efficiency (energy dissipation less than 1pJ per conversion step). Such ΔΣ ADCs are attractive for emerging broadband communication applications.

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“…6 achieved a figureof-merit of 0.7 pJ/step [23]. High-order multibit ΔΣ modulator with FIR NTF and unity-gain STF [14].…”

Section: High-order Multibit Single-stage δς Modulatorsmentioning

confidence: 99%

Delta-Sigma Modulators for Power-Efficient A/D Conversion in High-Speed Wireless Communications

Hamoui

Maloberti

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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“…Sigma-Delta (ΣΔ) architectures, either continuous-time (CT) [3] or switched-capacitor (SC) [4][5][6] can simultaneously achieve high BW, high resolution, and low power. Multi-bit SC implementations of ΣΔ modulators (ΣΔM) can reach FM 1 of the order of 0.5 pJ to 0.7 pJ [4][5][6] and FM 2 =0.54 pJ .…”

Section: Introductionmentioning

confidence: 99%

“…Multi-bit SC implementations of ΣΔ modulators (ΣΔM) can reach FM 1 of the order of 0.5 pJ to 0.7 pJ [4][5][6] and FM 2 =0.54 pJ . mm 2 is obtained in [4]; however, the decimation filter is not taken into account.…”

Section: Introductionmentioning

confidence: 99%

Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC

Esperanca

Goes

Tavares

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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-This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm 2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of -79 dB and an ENOB better than 12 bits can be reached without self-calibration.

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“…This results in a relaxed speed requirement and robust operation. The structure is similar to the one described in [3] where the feedback timing is relaxed in a singlesampled DS modulator. However, in a double-sampled modulator, the integrators should preferably include a full cycle delay, since this allows each integrator to settle independently.…”

mentioning

confidence: 99%

“…However, in a double-sampled modulator, the integrators should preferably include a full cycle delay, since this allows each integrator to settle independently. As a result, the topology of [3] cannot be directly applied to a double-sampled DS modulator. In Fig.…”

mentioning

confidence: 99%

Double-sampled ΔΣ modulator with relaxed feedback timing

Shen

Temes

2009

Electron. Lett.

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A double-sampled delta-sigma (DS) modulator topology is proposed that can relax the critical timing constraints in the modulator feedback path. The speed requirements of the quantiser and dynamic element matching logic are thus greatly reduced. To verify the effectiveness of the proposed topology, a second-order double-sampled DS modulator is designed and simulated.Introduction: With the continued downscaling of CMOS technology, delta-sigma (DS) analogue-to-digital converters are becoming popular in wideband applications such as wireless communication systems, high-definition television, medical imaging, etc. There are two possible realisations of a DS modulator. One is based on discrete-time (DT) switched-capacitor (SC) circuitry, which is traditionally used to achieve high resolution within low signal bandwidth. The other one employs continuous-time (CT) circuitry. Owing to the exponential settling nature of its internal integrators, the maximum permissible sampling frequency of a DT DS modulator is lower than its CT counterpart in the same process technology, especially when low power consumption is required. As a consequence, the most recently published DS ADCs incorporate CT modulators when the signal bandwidth is 10 MHz or higher [1]. However, compared to a CT modulator, a DT modulator offers several advantages: 1. its performance is less sensitive to clock jitter; 2. the signal transfer function (STF) and noise transfer function (NTF) is implemented by capacitance ratios, which can be very accurate in modern CMOS technology; 3. it is easy to scale the sampling frequency, which makes multi-standard applications possible; 4. design methodology for DT modulators is well established. To take advantage of DT modulators in a wideband ADC, the sampling frequency of a DT modulator must be increased. Double sampling is a powerful technique to achieve an effective sampling frequency that is twice as high as the actual modulator clock frequency. However, since the two clock phases are no longer distinguishable, the quantisation operation must be performed during the non-overlapping time interval of the clocks, which requires fast circuitry. This situation gets even worse if a multi-bit quantiser with dynamic element matching (DEM) is used. Then, the required speed for the quantiser and DEM logic should be much higher than that of the rest of the DS modulator. In this Letter, a novel double-sampled DS modulator topology is proposed which eliminates this critical timing constraint.

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An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers

Cited by 20 publications

References 4 publications

Delta-Sigma Modulators for Power-Efficient A/D Conversion in High-Speed Wireless Communications

Delta-Sigma Modulators for Power-Efficient A/D Conversion in High-Speed Wireless Communications

Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC

Double-sampled ΔΣ modulator with relaxed feedback timing

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