An 800 mA load current LDO with wide input voltage range

Yin, Jiaqi; Huang, Shanzhou; Duan, Quanzhen; Cheng, Yaping

doi:10.1109/iccds.2017.8120473

Cited by 21 publications

(7 citation statements)

References 6 publications

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“…Designing an LDO for wide load variations [21][22][23][24][25][26] is challenging because of the trade-off between input frequency and ripple. A high input frequency allows for a quick response to large load changes, but it also results in higher current consumption and lower current efficiency.…”

Section: Architecture and Principle Of The Proposed Ldomentioning

confidence: 99%

A high-efficiency and wide-load current range LDO with dynamic loop gain control technique

Lo,

Chiu,

Lin

et al. 2024

Jpn. J. Appl. Phys.

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The design proposes a low-dropout regulator (LDO) incorporating dynamic loop gain control to accommodate a wide load current range. It introduces a multi-phase error detection mechanism, a tri-state damping selector, and a dynamic integration shift register. These elements predict load variations and dynamically increase loop gain when the load variation is significant, all without increasing the input clock. This approach achieves a fast response and low power consumption simultaneously. The chip was implemented in 0.18-µm CMOS, with an input operating voltage of 1.2 V and an output voltage of 1 V. The measured results revealed that it could provide output currents from 0.5 mA to 150 mA, indicating that it had a 300 times wider current range. The maximum current efficiency was 99.93%, and the core area was 0.198 mm2.

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Section: Architecture and Principle Of The Proposed Ldomentioning

confidence: 99%

A high-efficiency and wide-load current range LDO with dynamic loop gain control technique

Lo,

Chiu,

Lin

et al. 2024

Jpn. J. Appl. Phys.

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“…It employs a dynamic compensation scheme where a resistance adjustment compensation network generates a zero to cancel the pole at the output of LDO. Another HV LDO proposed by Yin et al 17 comprises two cascaded LDOs. The first stage converts a wide input voltage (3.9–20 V) to a stable output voltage of 3 V and the second LDO stage increases its current driving capability by employing an NPN power transistor.…”

Section: Introductionmentioning

confidence: 99%

On‐chip bias‐generating architecture for an automotive application with a wide input dynamic range

Deo

Patra

Maity

et al. 2023

Circuit Theory & Apps

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SummaryThis paper presents an on‐chip bias‐generating architecture for automotive applications with a wide input range of 3.8–36 V in a 0.18‐ m high‐voltage bipolar‐CMOS‐DMOS (BCD) process. The proposed architecture effectively manages high‐voltage stress issues with few high‐voltage devices optimizing the silicon area. The proposed bias‐generator comprising crude‐reference and crude‐regulator generates a preliminary low bias voltage for the bandgap‐reference circuit. An adaptive‐biased, with‐capacitor, low‐dropout regulator generates a well‐regulated core supply with low quiescent current and better stability over the wide input range. The adaptive biasing expands the unity gain frequency with increasing load enabling a fast‐transient response. The proposed LDO provides a 5‐V output voltage and a load current of 10 A to 20 mA from 5.5‐ to 36‐V supply with a 500‐mV dropout voltage consuming a very low quiescent current of 5 A. With 0‐ to 20‐mA load step and an output capacitor of 1 F, an undershoot of 40 mV and an overshoot of 55 mV are achieved.

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“…For this purpose, The LDO regulators are commonly used for the stable operation and the power management of various mobile applications. As mobile devices continue to become smaller and more integrated, interest in capacitor-less LDO regulators is increasing [1,2,3,4,5,6,7]. In addition, the capacitor-less has the advantage of reducing the PCB board space, and must have a function to ensure the stability of the internal system for stable operation.…”

Section: Introductionmentioning

confidence: 99%

Design of capless LDO regulator with low voltage application based ESD protection circuit using SR-latch switch structure

Kwon

Koo

2022

IEICE Electron. Express

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The transient response characteristics such as overshoot and undershoot can be affected by the external capacitors of the LDO regulator. However, the capacitor-less LDO regulator proposed in this paper has an SR-Latch switch structure applied to the output terminal and gate terminal of the pass transistor in order to achieve improved transient response and secure excellent current driving capability. In addition, the proposed ESD protection device uses Penta-Well in low voltage applications embedded in the output stage and power line based on SCR (Silicon Control Rectifier) to provide improved ESD robustness characteristics. As a result, the transient response characteristics of the proposed LDO regulator with the SR-Latch switch structure were improved and the quiescent current was secured. The operating conditions of the proposed LDO regulator with the SR-Latch switch structure were set to an input voltage of 3.3V to 4.5V, maximum load current of 250mA, and an output voltage of 3V. As a result of the measurement, it was confirmed that the proposed LDO regulator maintained an undershoot voltage of 42 mV and an overshoot voltage of 31 mV when a load current of 250 mA was applied. In addition, HBM ESD robustness is guaranteed at 6kV.

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An 800 mA load current LDO with wide input voltage range

Cited by 21 publications

References 6 publications

A high-efficiency and wide-load current range LDO with dynamic loop gain control technique

A high-efficiency and wide-load current range LDO with dynamic loop gain control technique

On‐chip bias‐generating architecture for an automotive application with a wide input dynamic range

Design of capless LDO regulator with low voltage application based ESD protection circuit using SR-latch switch structure

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