An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With −93-dB THD+N, 113-dB SNR, and 93% Efficiency

Matamura, Atsushi; Nishimura, Naoaki; Birdsong, Preston; Bandyopadhyay, Abhishek; Spirer, Adam; Markova, Mariana; Liu, Shaolong

doi:10.1109/jssc.2021.3100548

Cited by 7 publications

(2 citation statements)

References 14 publications

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“…Power converters are ubiquitous in industrial and consumer electronics. They are employed in so many applications, from smartphones, tablets, and headphones [3], [4], to TV sets, car electronics, wireless power chargers for electric vehicle [5], [6], public fitness equipment [7], and wearable medical devices [8]. Power converters, such as DC-DC converters, bridges (half and full), and class-D power amplifiers, must present high efficiency and power density [9]- [12].…”

Section: Introductionmentioning

confidence: 99%

A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters

Karimi
¹
,

Ali
²
,

Aghajani
³

et al. 2022

IEEE Trans. Circuits Syst. I

6
0
0
0

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This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads (C L ) and operating frequencies ( f s ). The circuit consumed a power between 610 µW and 850 µW across the measured deadtime ranges while C L = 12 pF, V dd = 3.3 V, and f s = 200 kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of 150µ m × 260µm. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum T DLH and optimal T DHL at I Load = 25 mA is improved by 12% compared to a converter with a fixed deadtime of T DLH = T DHL = 12 ns.

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Section: Introductionmentioning
confidence: 99%

A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters
Karimi
¹
,
Ali
²
,
Aghajani
³

et al. 2022
IEEE Trans. Circuits Syst. I
6
0
0
0
View full text Add to dashboard Cite

show abstract

“…In high-end applications, audio digital-to-analog converters (DACs) with a dynamic range (DR) of above 130 dB are commercially available [1], [2], [3], [4], matching that of the human ear. However, the DR of typical monolithic class-D audio amplifiers is much lower, only around 110 dB for analog-input designs [5], [6], [7], [8], [9], [10] and up to about 115 dB for digital-input designs [11], [12], [13], [14].…”

mentioning
confidence: 99%

A 121.4-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier
Zhang
¹
,
Berkhout²,
Makinwa
³

et al. 2022
IEEE J. Solid-State Circuits
7
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2
0
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This article presents a class-D amplifier (CDA) with high dynamic range (DR). To eliminate the typically dominant noise contribution of a resistive feedback network, the input and feedback signals are chopped and applied to a capacitive feedback network. However, this leads to high-voltage (HV) transients at the input of the loop filter, which, due to timing and impedance mismatch in the chopped feedback network, could degrade linearity and even overstress low-voltage (LV) core devices. Robust processing of the HV chopped feedback signal is guaranteed with chopper timing skew correction, chopper impedance matching, and deadbanding. The prototype, implemented in a 180-nm bipolar-CMOS-DMOS (BCD) process, achieves 121.4 dB of DR, 5.9 dB higher than state-of-the-art closed-loop CDAs, and 8-μV RMS output-referred noise (A-weighted). It also achieves a peak total harmonic distortion (THD) + N of −109.8 dB and a peak efficiency of 93%/88% while driving 15 W/26 W into an 8-/4-load.

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Measuring station for testing on-ear headphones, made by 3D printing used in Industry 4.0
Pecolt,
Błażejewski,
Królikowski
et al. 2023
Procedia Computer Science
0
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0
0
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An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With −93-dB THD+N, 113-dB SNR, and 93% Efficiency

Cited by 7 publications

References 14 publications

A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters

A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters

A 121.4-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier

Measuring station for testing on-ear headphones, made by 3D printing used in Industry 4.0

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