2012 Symposium on VLSI Circuits (VLSIC) 2012
DOI: 10.1109/vlsic.2012.6243841
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An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration

Seung−Chul Lee
1
,
Brian Elies2,
Yun Chiu3
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