In this paper, transistor-level simulations of a detector called "cross-differentiate-multiplier demodulator (CDM)" are presented. This detector, which uses three blocks (a differentiator, a multiplier and a subtractor), is able to demodulate a received bit sequence, that was transmitted using a frequency-shift keying modulation scheme, with a bit rate equal to 20kbps. The application of this detector will be in a wireless sensor receiver operating in the 863-870MHz ISM band. In this sensor, a frequency hopping spread spectrum is used as modulation technology and Zigbee (IEEE 802.15.4) as the communication protocol. Design is performed using 0.35µm CMOS technology and a 3V supply. A comparison between the performances of different architectures studied, mainly in terms of BER, is presented at the end of this document.