An 8B/10B encoder with 2GHz operating frequency

Ashrafi, H.; Mousazadeh, Morteza; Hadidi, Khayrollah

doi:10.1109/mwscas.2016.7870005

Cited by 2 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When the 10-bits code group has ones more than zeros or zeros more than ones then the disparity output must be flipped, and that 10-bits code group has no disparity error, when 10-bits code is neutral then the disparity output is equivalent to disparity input and that 10-bits code has no disparity error, otherwise it has disparity error [10].The VHDL model of decoder is shown in Fig. 12.…”

Section: B/ 8b Decodingmentioning

confidence: 99%

FPGA implementation of 1000base-x Ethernet physical layer core

Salem

Zekry

Labeb

et al. 2018

IJET

View full text Add to dashboard Cite

This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

show abstract

Section: B/ 8b Decodingmentioning

confidence: 99%

FPGA implementation of 1000base-x Ethernet physical layer core

Salem

Zekry

Labeb

et al. 2018

IJET

View full text Add to dashboard Cite

show abstract

“…In serial data transmission systems, there is no strict limit to the number of "0" and "1". When consecutive, the voltage fluctuates, which can seriously affect the signal's integrity and cause electromagnetic interference to the system [1] . Albert X. Widner proposed the 8B/10B coding method and Peter A. Franaszek in 1983, which allows 8bit data in any data mode to be coded as 10bit data without D.C. components [2] .…”

Section: Introductionmentioning

confidence: 99%

“…But the single-byte coding speed of such designs still fails to meet the 1GHz application requirements. In the literature [1], a 2GHz encoder design was implemented in a 0.18μm process by using a combination of logic operations and lookup tables, with a special structure for the flip-flop and MOS circuit [1] . The design has a high area of 5080 μm 2 and consumes 9.38 mW of power, making it overly resource-intensive and under-versatile.…”

Section: Introductionmentioning

confidence: 99%

An 8B/10B parallel encoder design for the polarity pre-processing

Song

Yin

Zhao

et al. 2023

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

To tackle the high latency and slow encoding speed of 8B/10B encoder circuits in high-speed serial interfaces, a parallel structure for polarity pre-processing based on logic operations is proposed to optimize encoder performance in this article. Firstly, the encoding process is divided into polarity pre-processing and coding two pipeline stages. This method equals each stage’s delay and decreases the coding waiting period. Additionally, the structure employs polarity pre-processing to optimize the critical delay paths into multi-stage heterodyne gates in series. Therefore, the effect of the number of input bytes on the critical delay path can be significantly reduced. The effectiveness of our proposed encoder is demonstrated to encode 4-byte loads by VCS simulation and synthesized using Synopsys’ Design Compiler tool upon the SMIC 65nm process. Results show that a high operating frequency of 909MHz with a 2245.68µm2 footprint area can be achieved. Compared with the cascaded and polarity-selective structures, the proposed framework has advantages in terms of speed and resource usage. These advantages greatly help to meet the high-speed transmission requirement.

show abstract

An 8B/10B encoder with 2GHz operating frequency

Cited by 2 publications

References 4 publications

FPGA implementation of 1000base-x Ethernet physical layer core

FPGA implementation of 1000base-x Ethernet physical layer core

An 8B/10B parallel encoder design for the polarity pre-processing

Contact Info

Product

Resources

About