An 8ns 256k Bicmos Ram

Abstract

A 256Kh ECL RAM achieving less than 400mW power consumption at 50MHz operation, and 150mW at standby will be descrihed in this paper. The RAM was fabricated using 1.Opm performance Bipolar CMOS (Hi-BiCMOS) technology. 64Kb ECL RAMS with access times of 5 to 7ns and 256Kb CMOS SRAM of 21ns were reported previously' ress access time and low-power consumption, an ECL-MOS level shifter and a powerdown circuit technique were developed. Figure 1 shows the 1.0p.m Hi-BiCMOS device structure. In the bipolar part of the device, parasitic capacitances are reduced by scaling. The polysilicon emitter structure has been employed to achieve a cutoff frequency of 9GHz. In the CMOS segment of the chip, the gate lengths were scaled to 0.9@ (N-channel) and 1.lp.m (P-channel) with 20nm gate oxide. The use of 1.0pm design rules permits layout of a memory cell with high-resistance polysilicon load in 57.4W2 and a chip in 4.09mm x 8.60mm. Basic characteristics of this device are shown in Table 1.A block diagram of the RAM is shown in Figure 2. An ECL input signal level is received by an input buffer and is shifted to a MOS signal level by an ECL-MOS level shifter. X and Y decoders select one memory cell in the memory cell array, divided into 8 blocks, to reduce propagation delay time (tpd) of a wordline and active power consumption of the memory cell array. This results in 400mW active power.main storage system using a large number of RAMs. When the chip select control signal CS is high, the chip is in a standby mode. Figure 3 shows the input buffer circuit, that consists of an ECL receiver and an ECL-MOS level shifter. The current control signal VB is connected to an NPN transistor base to control current of the ECL receiver. The VB is low in the standby mode so that the ECL current does not flow. The standby power is reduced to 150mW by this power-down technique.3. To achieve sub-10ns add-