2020
DOI: 10.1109/jestpe.2019.2944164
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An Active Voltage Balancing Control Based on Adjusting Driving Signal Time Delay for Series-Connected SiC MOSFETs

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Cited by 45 publications
(17 citation statements)
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“…The effect of the device-to-ground parasitic capacitance on the dynamic voltage sharing for the series-connected devices have already been discussed in the previous studies [13], [14], [34]- [38]. It is still necessary to make a summary of the effect in different switching scenarios, because it is the precondition of the proposed voltage balancing strategies.…”
Section: Root Cause Of the Unbalanced Voltage Sharing In Different Switching Scenariosmentioning
confidence: 99%
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“…The effect of the device-to-ground parasitic capacitance on the dynamic voltage sharing for the series-connected devices have already been discussed in the previous studies [13], [14], [34]- [38]. It is still necessary to make a summary of the effect in different switching scenarios, because it is the precondition of the proposed voltage balancing strategies.…”
Section: Root Cause Of the Unbalanced Voltage Sharing In Different Switching Scenariosmentioning
confidence: 99%
“…It should be mentioned that the resolution of the compensation pulsewidth is restricted by the controller minimum clock cycle. As mentioned earlier, the sub-nanosecond unit time step is required if the pulse-width is the only control freedom in the conventional voltage source gate driver [14], [33]. With the proposed approach, the compensation current magnitude can be set at a relatively small value.…”
Section: Voltage Balancing Strategies For Different Switching Scenariosmentioning
confidence: 99%
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