An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits

Srivastava, Ashok; Zhang, Chuang

doi:10.1080/15501320802001259

Cited by 17 publications

(7 citation statements)

References 7 publications

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“…Another implantation is then completed using a special doping type, with ions penetrating the gate oxide. The photo resist is stripped [4]. At some point during the consequent fabrication process, implanted ions are activated by annealing at an elevated temperature.…”

Section: Proposed Circuit Using Mtcmos Techniquementioning

confidence: 99%

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Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Gavaskar¹,

Thangaraj²

2019

IJCA

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SRAM is faster and more expensive and it is typically used for CPU cache. SRAMs are the fastest form of RAM available which does not need to be refreshed periodically. Here, 6T SRAM cell with O-ABB circuit is designed. On-chip adaptive body bias (O-ABB) circuit consists of standby leakage current (Iddq) sensor circuit, decision circuit and body bias control circuit which are used to compensate the effect of NBTI. Dynamic power is the power measured when circuit is in active mode. Here, Multi Threshold Complementary Metal Oxide Semiconductor (MTCMOS) technology is applied in the individual circuit of On-chip adaptive body bias to decrease the power. Low power MTCMOS methodology is applied in the proposed circuit which provides high performance and low power design. Design metrics such as Power, Delay and Power delay product are taken in to account. After applying MTCMOS technology, the power and the power delay product of the proposed circuit decreases when compared the existing circuit. All the circuits were designed using SYNOPSYS EDA tool and simulated in 28nm technology.

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Section: Proposed Circuit Using Mtcmos Techniquementioning

confidence: 99%

“…Very large scale integration (VLSI) is the technique of generate an integrated circuit (IC) by combining thousands of transistors into a single chip. The microprocessor is a VLSI device [4]. Earlier than the beginning of VLSI technology the majority ICs had a limited set of functions they could execute.…”

Section: Introductionmentioning

confidence: 99%

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Gavaskar¹,

Thangaraj²

2019

IJCA

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“…In other words, applying a large V BS , the source‐body junction may turn on, and a dc current flows across the P–N junction with an exponential dependence on the body voltage. It is noted that, in order to avoid latch up, the source‐body voltage should be set to below 0.4 V . In the proposed design, the body terminal of the NMOS transistor is connected to the body voltage V B of 0.38 V, which is lower than the turn‐on voltage of P–N junction, and the leakage current is negligible.…”

Section: Principles Of the Proposed Distributed Amplifier Designmentioning

confidence: 99%

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

Saadi

Hakimi

2016

Circuit Theory & Apps

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Summary This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.

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“…The threshold voltage is increased when the source-to-substrate p-n junction of a MOSFET is reverse biased. The threshold voltage of a MOSFET can also be reduced by forward biasing the source-to substrate p-n junction [13]. Among the leakage power reduction techniques, RBB technique, which increases the threshold voltage (Vth) of transistors and are extensively employed to suppress the sub-threshold leakage current (ISUB) as depicted in Figs.…”

Section: Effect Of Body Biasing On Threshold Voltage Leakage Commentioning

confidence: 99%

Temperature Aware Design for High Performance Processors

Mustafa¹,

İbrahim

Sulaiman

et al. 2015

The 7th International Conference on Information Technology

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Abstract-efficient temperature aware design in modern microprocessors, especially in the design of digital portable, notebook, and handheld computers is becoming increasingly important. Many studies have been done on microprocessor's dynamic thermal management techniques and methodologies; from thermal estimation to voltage scaling, clock gating, and total/active power monitoring and control. As technology, moves into deep submicron feature sizes and the leakage power are expected to increase because of the exponential increase in leakage currents with technology scaling. In nanometer technologies, it is observed that leakage power will become comparable to dynamic or total power dissipation in the next generation processors in the next few years. This paper presents a hardware design for dynamic thermal management strategies for microprocessors leakage power control, which is particularly appealing for portable and embedded systems. LTspice simulation program is used to verify the theoretical idea and confirm the design operations. Results shows that, the appropriate thermal management system can be designed for a much lower maximum power rating with minimal performance impact for typical applications, considerable amount of power consumption reduction as well as thermal aware challenges have been obtained.

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An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits

Cited by 17 publications

References 7 publications

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

Temperature Aware Design for High Performance Processors

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