An adaptive congestion-aware routing algorithm for mesh network-on-chip platform

Huang, Po-Tsang; Hwang, Wei

doi:10.1109/soccon.2009.5398015

Cited by 12 publications

(8 citation statements)

References 4 publications

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“…Second, an incoming packet cannot be assigned to a buffer that already holds a packet with the same departure time. Additionally, different buffer architectures are also evaluated with different routing algorithms, including XY routing, DyXY [36] and an adaptive routing [37]. Moreover, the proposed data-linked two-level FIFO buffer is implemented using UMC 65 nm standard performance CMOS technology to demonstrate the power consumption and area.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…18 presents the average latency under different routing algorithms with the middle buffer and fully associated two-level FIFO buffer architectures. The routing algorithms are XY routing and DyXY [36] routing algorithms and an adaptive congestion-aware routing algorithm [37]. In DyXY and adaptive routing algorithms, the two-level FIFO buffer uses the TDMA arbiter described in Sect.…”

Section: Performance Evaluationmentioning

confidence: 99%

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Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks

Huang

Hwang

2011

IEICE Trans. Fundamentals

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The on-chip interconnection network (OCIN) is an integrated solution for system-on-chip (SoC) designs. The buffer architecture and size, however, dominate the performance of OCINs and affect the design of routers. This work analyzes different buffer architectures and uses a data-link two-level FIFO (first-in first-out) buffer architecture to implement high-performance routers. The concepts of shared buffers and multiple accesses for buffers are developed using the two-level FIFO buffer architecture. The proposed two-level FIFO buffer architecture increases the utilities of the storage elements via the centralized buffer organization and reduces the area and power consumption of routers to achieve the same performance achieved by other buffer architectures. Depending on a cycleaccurate simulator, the proposed data-link two-level FIFO buffer can realize performance similar to that of the conventional virtual channels, while using 25% of the buffers. Consequently, the two-level FIFO buffer can achieve about 22% power reduction compared with the similar performance of the conventional virtual channels using UMC 65 nm CMOS technology. key words: two-level FIFO buffer, centralized shared buffer, router, on-chip interconnection network

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Performance Evaluationmentioning

confidence: 99%

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks

Huang

Hwang

2011

IEICE Trans. Fundamentals

Self Cite

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“…Recent studies [3], [12], [15] showed that local congestion has a significant impact on network performance. Data transmission between source to destination nodes can suffer with high latency if congestion is encountered.…”

Section: A Congestion and Effects On Noc Performancementioning

confidence: 99%

Predicting Networks-on-Chip traffic congestion with Spiking Neural Networks

Javed

Harkin

McDaid

et al. 2021

Journal of Parallel and Distributed Computing

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“…Some algorithms uses multiple information to process congestion. The Path-Congestion Aware Adaptive Routing (PCAR) and an upgraded Odd-Even adaptive routing algorithm both use switch contention along with buffer occupancy levels to route data through a least congested path [18]. Above mentioned techniques are reactive to congestion and only react when it detects on-path congestion.…”

Section: Background and Related Workmentioning

confidence: 99%

Exploring Spiking Neural Networks for Prediction of Traffic Congestion in Networks-on-Chip

Javed

Harkin

McDaid

et al. 2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

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Networks-on-Chip (NoC) is the most modular and scalable solution for next generation hardware communication where significant data traffic loads are shared across many communication paths. One key challenge in maximising NoC performance is traffic congestion. The management of congestion at the earliest stage can significantly minimize the impact on NoC throughput. Prediction of NoC congestion offers a pre-emptive strategy in maximising NoC throughput. This paper proposes a novel spiking neural network (SNN) approach to prediction of traffic congestion. The proposed SNN exploits the temporal nature of the traffic to identify congestion patterns. The proposed SNN explores two models and both are trained and evaluated to predict local congestion 30 clock cycles in advance of occurring. Results shows that the SNN predictor utilizes 9 times less hardware area than previous approaches and can achieved up to 96.59% in accuracy.

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An adaptive congestion-aware routing algorithm for mesh network-on-chip platform

Cited by 12 publications

References 4 publications

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks

Predicting Networks-on-Chip traffic congestion with Spiking Neural Networks

Exploring Spiking Neural Networks for Prediction of Traffic Congestion in Networks-on-Chip

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