An Adaptive Fault-Tolerant and Congestion Controlled Selection Strategy for Networks on Chip

Abstract

Networks on chip are being developed as a communication infrastructure in the design of Multiprocessor SOCs. With the reduction in feature size, transient faults on the links are becoming a major issue on the performance of NOCs. In this paper, two fault-tolerant algorithms are proposed. In the first algorithm, a faulty link tolerant algorithm is designed which by measuring network loads on the links will reduce transient faults and balances the load. To address the effect of hardware faults, fault and congestion controlled algorithm is designed that not only control the congestion, but also the faults on both links and the nodes. The proposed strategies are evaluated on two different synthetic traffic patterns and the results so obtained shows better network and hardware performance of both the routing in comparison with non-fault-tolerant routing.