2023
DOI: 10.1002/cta.3616
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An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects

Abstract: SummaryThis work proposes a link training based half‐rate dynamic current‐steering echo‐cancellation hybrid circuit topology for full‐duplex signaling that performs echo cancellation by deploying a bit error detection unit and backchannel adaptation. In addition, this work proposes a power‐efficient half‐rate dynamic current‐steering logic hybrid circuit for full‐duplex signaling over on‐chip interconnects for simultaneous transmission and reception. The half‐rate dynamic current‐steering hybrid circuit topolo… Show more

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