An Adaptively Biased LDO Regulator with 11nA Quiescent Current and 50mA Available Load

Li, Jing; Li, Jiping; Zhang, Jianyu; He, Yu; Qiuzhen, XU; Qu, Pengda; Hu, Wei-Wen; Xiao, Zhiming

doi:10.1109/iscas51556.2021.9401687

Cited by 10 publications

(3 citation statements)

References 13 publications

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“…If a speed up of the transient response is desired, the biasing current I biasSSF can be raised to make the AVDM circuit faster, thus improving the transient response of the overall LDO and reducing the FoM t . Furthermore, our implementation keeps the quiescent current consumption roughly constant regardless of the load current, unlike [17], [21] and [22] where I Q depends on I L to a greater or lesser degree.…”

Section: Resultsmentioning

confidence: 99%

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

Pereira-Rial

López

Carrillo

et al. 2022

IEEE Trans. Circuits Syst. II

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This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 -11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO's error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.

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Section: Resultsmentioning

confidence: 99%

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

Pereira-Rial

López

Carrillo

et al. 2022

IEEE Trans. Circuits Syst. II

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“…However, the speed of the buffer needs to be fast enough, which means a certain amount of current still needs to be consumed in the buffer. Adaptive biasing techniques are proposed to scale the bias current of EA (IBIAS) proportional to load current (ILOAD) [23,24,25,26]. Under heavy load, a larger loop bandwidth and a higher slew rate can be achieved, which make the recovery time and overshoot be reduced under full-load to no-load transition.…”

Section: Introductionmentioning

confidence: 99%

Design of 300nA quiescent current and 300mA load capacity LDO with fast transient response

Yu,

Gao,

Zhang

et al. 2024

IEICE Electron. Express

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This paper presents a low dropout regulator (LDO) with a low quiescent current which helps to extend the standby time of battery-powered electronic devices. By utilizing the switchable bias technique in the error amplifier (EA), the bias current is switched to a higher level to accelerate the transient response under heavy load, while a low bias current is applied to EA to maintain a low quiescent current under light load. High speed current comparators and hysteresis control are combined to ensure fast and stable switching operation of the bias current. Moreover, an inrush current suppression circuit is proposed by recycling the switchable bias in EA. During startup, the bias current of EA can be kept low, and a reduced slew rate can be obtained at the pass gate voltage. The proposed LDO has been fabricated in 0.18-μm CMOS process, The experimental total quiescent current is 300nA under no-load condition. The maximum load current is 300mA. Measurement results show that the LDO can be settled within 8μs for a load current step of 0-50mA. In the startup process, the measured inrush current can be effectively limited.

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“…Nevertheless, the inherent ripple superimposed to the generated voltage results critical for high-performance analog frontends [5]. Therefore, a low-dropout (LDO) regulator may be used to generate the required spurious-free and stable supply voltage [5]- [45]. Besides, capacitor-less (CL) LDOs result very compact and suitable to reduce the cost of the prototype, as the internal compensation of its frequency response allows avoiding the use of bulky off-chip load capacitors [23].…”

mentioning

confidence: 99%

0.6-V-V _IN 7.0-nA-I _Q 0.75-mA-I _L CMOS Capacitor-Less LDO for Low-Voltage Micro-Energy-Harvested Supplies

Pereira-Rial

López

Carrillo

2022

IEEE Trans. Circuits Syst. I

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A capacitor-less (CL) low-dropout (LDO) regulator suitable to be incorporated in an on-chip system with low-voltage micro-energy-harvested supply, is proposed in this contribution. The differential input stage of the error amplifier includes bulk-driven MOS transistors, thus providing the LDO with an output voltage range that extends from the negative rail up to a level very close to the input voltage without the need of using a resistive feedback network. The circuit parameters relying on the feedback factor, β, are maximized thanks to the use of a unitary value for this parameter. The CL-LDO has been designed and fabricated in standard 180-nm CMOS technology and optimized to operate with an input voltage equal to 0.6 V and a reference level of 0.5 V. The experimental characterization of the fabricated prototypes shows that, under these operating conditions, the LDO is able to deliver a load current above 0.75 mA with a total quiescent current of only 7.0 nA. Furthermore, the proposed voltage regulator is able to operate from input voltages as low as 0.4 V, delivering in this case a maximum load current of 30 μA.

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An Adaptively Biased LDO Regulator with 11nA Quiescent Current and 50mA Available Load

Cited by 10 publications

References 13 publications

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

Design of 300nA quiescent current and 300mA load capacity LDO with fast transient response

0.6-V-V _IN 7.0-nA-I _Q 0.75-mA-I _L CMOS Capacitor-Less LDO for Low-Voltage Micro-Energy-Harvested Supplies

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An Adaptively Biased LDO Regulator with 11nA Quiescent Current and 50mA Available Load

Cited by 10 publications

References 13 publications

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

Design of 300nA quiescent current and 300mA load capacity LDO with fast transient response

0.6-V-V IN 7.0-nA-I Q 0.75-mA-I L CMOS Capacitor-Less LDO for Low-Voltage Micro-Energy-Harvested Supplies

Contact Info

Product

Resources

About

0.6-V-V _IN 7.0-nA-I _Q 0.75-mA-I _L CMOS Capacitor-Less LDO for Low-Voltage Micro-Energy-Harvested Supplies