An advanced BiCMOS process utilizing ultra-thin silicon epitaxy over arsenic buried layers

El-Diwany, M.; Borland, John; Chen, J.; Hu, Song; Wijnen, P. van; Vorst, C.; Akylas, V.; Brassington, M.P.; Razouk, R. R.

doi:10.1109/iedm.1989.74271

Cited by 9 publications

(1 citation statement)

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“…Analog requirements differ in that design rules do not have to be scaled as aggressively; 1.5 -2 p rules suffice for most applications. The challenge of analog is in achieving the proper balance between digital and analog requirements.Numerous approaches to implementing a BiCMOS process have been presented[1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. A simplified process step sequence comparing BiCMOS to CMOS and Bipolar process flows is shown inTable 111.…”

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confidence: 99%

An overview of BiCMOS technology and applications

Alvarez¹,

Pai²,

Ratnakumar³

et al.

IEEE International Symposium on Circuits and Systems

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BiCMOS technology significantly enhances speed performance while incurring a negligible power or area penalty. Thus BiCMOS can provide applications with CMOS power and densities at speeds which were previously the exclusive domain of bipolar, This has been demonstrated in applications ranging from static RAMS to gate arrays to microprocessors.Thus the concept of a "system on a chip" becomes a reality with BiCMOS.The main disadvantage of BiCMOS is greater process complexity, which results in a 1.1-1.3X packaged chip cost. BiCMOS is now being demonstrated at 0.5p.m. This will extend the conventional 15VI TTL and ECL interfaces another generation of technology. The BiCMOS challenge has shifted from process and technology to circuits and systems.

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