An Agile Approach to Building RISC-V Microprocessors

Lee, Yunsup; Waterman, Andrew; Cook, Henry; Zimmer, Brian; Keller, Ben; Puggelli, Alberto; Kwak, Jaehwa; Jevtić, Ruzica; Bailey, Stevo; Blagojević, Milovan; Chiu, Pi-Feng; Avizienis, Rimas; Richards, Brian; Bachrach, Jonathan; Patterson, David A.; Alon, Elad; Nikolić, Borivoje; Asanović, Krste

doi:10.1109/mm.2016.11

Cited by 93 publications

(28 citation statements)

References 9 publications

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“…With the trend and opportunities in domain-specific architectures [20] , e.g., open-source implementations and agile chip development technics [22] , customized graph processing accelerators have emerged as a promising solution to achieve both high performance and energy efficiency.…”

Section: Discussionmentioning

confidence: 99%

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A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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Graph is a well known data structure to represent the associated relationships in a variety of applications, e.g., data science and machine learning. Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred to as graph processing accelerators, are essential and emerging to provide the benefits significantly beyond those pure software solutions can offer. In this paper, we conduct a systematical survey regarding the design and implementation of graph processing accelerator. Specifically, we review the relevant techniques in three core components toward a graph processing accelerator: preprocessing, parallel graph computation and runtime scheduling. We also examine the benchmarks and results in existing studies for evaluating a graph processing accelerator. Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations. We finially present to discuss several challenges in details, and to further explore the opportunities for the future research.

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Section: Discussionmentioning

confidence: 99%

“…FPGAs have been widely adopted in industries to accelerate the datacenter [23] for the high energy efficiency and performance. ment of FPGA graph processing accelerators [22] .…”

Section: Opportunitiesmentioning

confidence: 99%

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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“…The tool consists of a set of parameterized libraries that can be used to generate different types of SoC. By standardizing the interfaces used to connect generators of different libraries to each other, it creates a plug-and-play environment, which makes it easy to change hardware components without the need to change the source code of each one [13]. The generators available are listed as follows:…”

Section: Rocket Chip Generatormentioning

confidence: 99%

Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator

Neves¹

2018

JCP

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This article presents the analysis and comparison of two powerful tools to explore design space and study multi-core microprocessors. Heracles, developed at the MIT, is a modular tool to create MIPS multi-core processors. Its modularity allows quick development by varying the types of processor, memory, network interconnect and cache. RISC-V is a new instruction set architecture, developed at the University of California, Berkeley, that has several tools for designing architectures and processors that use this instruction set. The Rocket Chip Generator is one of these tools. It is the equivalent of Heracles for the MIPS architecture and, as such, provide several features that allows rapid development of RISC-V multi-core processors. We compared the target hardware and software features of these tools. The Rocket Chip Generator proved to be an excellent tool for the development of new RISC-V processors whereas Heracles seemed a more adequate tool for teaching and parallel architecture research at higher levels of abstraction.

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“…In this work, we focus on the Chisel [3] HCL, which is quite mature and has been proven successful in the development of complex circuits, notably rocket-chip, the original RISC-V core generator [4] and Google Edge TPU (Tensor Processing Unit) [5]. Chisel was initially designed to gain agility in RISC-V microprocessors tape-out process [6]. Despite this initial target, we also successfully use it into our production FPGAbased network functions at OVHcloud.…”

Section: Introductionmentioning

confidence: 99%

(System)Verilog to Chisel Translation for Faster Hardware Design

Bruant

Horrein²,

Müller

et al. 2020

2020 International Workshop on Rapid System Prototyping (RSP)

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Bringing agility to hardware developments has been a long-running goal for hardware communities struggling with limitations of current hardware description languages such as (System)Verilog or VHDL. The numerous recent Hardware Construction Languages such as Chisel are providing enhanced ways to design complex hardware architectures with notable academic and industrial successes. While the latter environments are now mature and perfectly suited for brand new projects, migrating partially or entirely existing Verilog code-base proves to be a challenging and very time-consuming process. Successful migrations need to be able to leverage finely tuned existing hardware descriptions as a basis to build complex systems through simple iterations. This article introduces sv2chisel, an open-source automated (System)Verilog to Chisel translator as entry point for this iterative migration processes. Our tool achieved the proper translation, with on-par resource usage of a real-world production FPGA design at OVHcloud as well as two independent open-source Verilog projects: a MIPS core and the size-optimized 32-bit RISC-V core PicoRV32.

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An Agile Approach to Building RISC-V Microprocessors

Cited by 93 publications

References 9 publications

A Survey on Graph Processing Accelerators: Challenges and Opportunities

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator

(System)Verilog to Chisel Translation for Faster Hardware Design

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