An algorithm for dc solutions in an experimental general purpose interactive circuit design program

Ho, Chung; Zein, D.A.; Ruehli, Albert E.; Brennan, P.A.

doi:10.1109/tcs.1977.1084366

Cited by 15 publications

(1 citation statement)

References 7 publications

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“…1) the setup and solution of the linearized modified nodal equations required for the analysis, 2) the partitioning of the original simulation problem into a collection of simpler problems which can be concurrently solved. The most essential routine in any circuit simulator devoted to the analysis of nonlinear circuits is the determination of at least a single DC solution [9], [10]. This solution may be used to establish a small-signal model suitable for AC analysis for a given circuit or can be used as initial condition which is congruent with the determination of its transient response through the integration of its associated differential-algebraic equations [11].…”

Section: Introductionmentioning

confidence: 99%

DC Large-Scale Simulation of Nonlinear Circuits on Parallel Processors

Udave

Ogrodzki²,

Anda

2012

International Journal of Electronics and Telecommunications

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Newton-Raphson DC analysis of large-scale nonlinear circuits may be an extremely time consuming process even if sparse matrix techniques and bypassing of nonlinear models calculation are used. A slight decrease in the time required for this task may be enabled on multi-core, multithread computers if the calculation of the mathematical models for the nonlinear elements as well as the stamp management of the sparse matrix entries is managed through concurrent processes. In this paper it is shown how the numerical complexity of this problem (and thus its solution time) can be further reduced via the circuit decomposition and parallel solution of blocks taking as a departure point the Bordered-Block Diagonal (BBD) matrix structure. This BBD-parallel approach may give a considerable profit though it is strongly dependent on the system topology. This paper presents a theoretical foundation of the algorithm, its implementation, and numerical complexity analysis in virtue of practical measurements of matrix operations.

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Section: Introductionmentioning

confidence: 99%

DC Large-Scale Simulation of Nonlinear Circuits on Parallel Processors

Udave

Ogrodzki²,

Anda

2012

International Journal of Electronics and Telecommunications

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show abstract

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2010

Circuit Simulation

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A method of analogue‐digital multiple fault diagnosis

Reisig

DeCarlo

1987

Circuit Theory & Apps

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SUMMARYThis paper develops an algorithm for multiple fault diagnosis of analogue-digital circuits. By sequentially partitioning the devices into those 'assumed good' and those 'under test', it is possible to develop a set of fault diagnosis equations which account for the special nature of digital components. A modified Newton-Raphson solution is then described which incorporates a digital state hypothesis testing scheme in the solution of the fault diagnosis equations for each partition. After solving for the input-output characteristics of the devices under test, a Boolean decision algorithm is used to analyse the test results of each partition and thus sequentially arrive at the set of faulty elements. A generic condition for diagnosability in terms of the circuit topology is given. Two examples are included to illustrate the technique.

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An algorithm for dc solutions in an experimental general purpose interactive circuit design program

Cited by 15 publications

References 7 publications

DC Large-Scale Simulation of Nonlinear Circuits on Parallel Processors

DC Large-Scale Simulation of Nonlinear Circuits on Parallel Processors

Bibliography

A method of analogue‐digital multiple fault diagnosis

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