An All-Digital, Cyclic and Synthesizable TDC in the ADPLL-Based Clocking Digital Systems for Multidomain Power Management

Abstract

In this paper, we propose an all-digital, cyclic and synthesizable TDC architecture, which may be used as a core block in ADPLLs to replace the analog block as a phase/frequency detector and a charge pump. Traditional designs of the DVFS scheme for multidomain power management are based on a conventional analog PLL to generate the dynamic voltage and frequency in which the use of a digital TDC eliminates the need for current sources in conventional analog PLLs.