An all-digital phase-locked loop for high-speed clock generation

Chung, Ching-Che; Lee, Chen‐Yi

doi:10.1109/jssc.2002.807398

Cited by 182 publications

(15 citation statements)

References 9 publications

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“…Table 1 shows the comparison results of the various delay techniques in a 55-nm CMOS process. In [23,24] the INV and AND logic gate take power in the range of 90-to-80 µW. The size is because of 800 transistors.…”

Section: Proposed Ihdc-based Dpwmmentioning

confidence: 99%

Single Inductor-Multiple Output DPWM DC-DC Boost Converter with a High Efficiency and Small Area

Park

Khan

et al. 2018

Energies

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In this paper, a small-area and high-efficiency single-inductor multiple output (SIMO) boost converter with digital pulse-width modulation (DPWM) is proposed. The DPWM comprises a delay line using interlaced hysteresis delay cells (IHDCs) that occupy a small area while consuming a low power amount. These proposed IHDCs are applied to replace the conventional delay cells of the prior works for both the power and area reductions. Regarding the DC-DC converter, this technique comprises fewer digital blocks in the feedback path compared with the conventional DC-DC converter, and the DPWM architecture uses IHDCs. The purpose of the digital limiter block is to concede some helpful code for the DPWM. The IHDC topology used for delay in DPWM is of the simplest architecture. The high-side power switch gate drivers need individual phases which are generated by phase control. The Complementary Metal Oxide Semiconductor (CMOS)-fabrication process is 55 nm, with a standard supply voltage of 1.8 V and outputs of 2.2 and 2.4 V. The chip area is approximately 170 × 190 µm and its efficiency is 94.4%.

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Section: Proposed Ihdc-based Dpwmmentioning

confidence: 99%

Single Inductor-Multiple Output DPWM DC-DC Boost Converter with a High Efficiency and Small Area

Park

Khan

et al. 2018

Energies

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“…CSI (Maymandi-Nejad and Sachdev 2003 ) 0.35 (El Mourabit et al 2012 ) 40 400 211 μW @ 400 MHz 450 μm 2 – – N/A Digital 4. Cascaded inverters (Ching-Che and Chen-Yi 2003 ) 0.35 5 300 950 μW @ 400 MHz 0.36 mm 2 – – N/A Digital …”

Section: Open Research Issues and Conclusionmentioning

confidence: 99%

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

et al. 2016

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A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

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“…To reduce the design cycle when a process or specification is changed, researchers have proposed numerous DCOs from standard cells [11,12,13,14]. Among these, driving capability modulation (DCM) changes the driving current of each delay cell by controlling the number of enabled tristate buffers/inverters [11].…”

Section: Review Of Conventional Dcosmentioning

confidence: 99%

“…Although the design concept of this approach is straightforward, the linearity and power consumption performances are poor, and the resolution is insufficient. Or-and-inverter (OAI) cells enhance the resolution by different input pattern combinations but do not resolve the poor linearity [12]. Although the digitally controlled varactor (DCV) has a good performance in both resolution and linearity [13], it is difficult to use a few cells to increase the range of operations.…”

Section: Review Of Conventional Dcosmentioning

confidence: 99%

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

Sheng

Hong

2016

Sensors

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This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

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An all-digital phase-locked loop for high-speed clock generation

Cited by 182 publications

References 9 publications

Single Inductor-Multiple Output DPWM DC-DC Boost Converter with a High Efficiency and Small Area

Single Inductor-Multiple Output DPWM DC-DC Boost Converter with a High Efficiency and Small Area

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

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