An all-digital synthesizable baseband for a delay-based LINC transmitter with reconfigurable resolution

Abstract

The linear amplification with nonlinear component transmitter is a promising solution to high efficiency and high linearity amplification for non-constant envelope signals. An all-digital synthesizable baseband for a delay-based LINC transmitter is implemented. This paper proposes a standard-cell based synthesizable methodology which can be applied in the ASIC process efficiently without performance degradation compared to the manual layout. A scheme to overcome the limited resolution of conventional phase detectors is proposed. It employs alternative phase detector structures to provide reconfigurability for higher resolution after fabricating, resulting in an 11 ps resolution improvement. Due to the PVT variation, an adaptive calibration scheme focusing on the inherent imbalance between two delay lines is depicted, which reveals an effective EVM enhancement of 5.37 dB. This baseband chip is implemented in 0.13 μm CMOS technology, and the transmitter with the baseband has an EVM of −28.96 dB and an ACPR of −29.51 dB, meeting the design requirement.

A high-linearity and high-resolution delay line structure with a calibration algorithm in delay-based LINC transmitters

“…As it is known from the technology library, the delay of a standard cell is a function of the transition of the input and the load capacitance, i.e. Cell_Delay D f .Input_Transition; Load_Capacitance/: (1) In this design, we choose CLKBUFX1 in the standard cell library as a basic delay cell, according to the detailed requirements described in Reference [10]. We have simulated its delay changing with input transition and load capacitance, as shown in Figure 4.…”

“…With the control code sweeping from zero to 16, the delay increment is measured, as shown in Figure 5. The design process needs a careful manual layout and iterative simulation, which is not practical for the all-digital flow in Reference [10]. Besides, a digital circuit is more robust to interference and yields better portability over different processes.…”

“…Before introducing the calibration algorithm, we need to describe the DCV structure which can be appended after the delay line to get a finer resolution, as depicted in Reference [10]. For practical consideration and design requirements, the maximum delay that the DCV can provide should cover at least a cell delay in the delay line.…”

“…Calibration needs a reference so we employ two delay lines in the calibration scheme which is available in the LINC transmitter where two modulation paths are necessary. The basic principle is to set some control code to delay line 1 and delay line 2 respectively, obtaining the delay difference between them by a simple DLL operation expressed in Reference [10]. Because the delay adjustment is realized by the DCV line, the delay difference is represented by F1 and E1 or F2 and E2.…”

“…The chip is the same with Reference [10] but with more testability. It is a totally digital synthesizable design by the IC Complier EDA tool.…”