An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS

Pamula, Venkata Rajesh; Sun, Xun; Kim, Sung Hoon; Rahman, Fahim; Zhang, Baosen; Sathe, Visvesh

doi:10.1109/vlsic.2018.8502375

Cited by 29 publications

(9 citation statements)

References 2 publications

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“…Many TRNG designs have been proposed that make use of a wide range of entropy sources, but none have yet been widely accepted as a solution for security concerns. One of the first entropy sources was thermal noise either extracted directly from a resistor 6 or through its effect on digital circuits such as the introduction of clock-jitter or meta-stability [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] . The weaknesses of the thermal noise-based designs are its sensitivity to noise-based attacks, compromising the randomness of the output, as well as issues with the design complexity required for post-processing and tuning of the system 10,[23][24][25][26] .…”

mentioning

confidence: 99%

Random-telegraph-noise-enabled true random number generator for hardware security

Brown

Zhang

Zhou

et al. 2020

Sci Rep

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The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multi-level and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.

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mentioning

confidence: 99%

Random-telegraph-noise-enabled true random number generator for hardware security

Brown

Zhang

Zhou

et al. 2020

Sci Rep

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“…Si based true random number generators (TRNGs) usually derive their randomness from thermal noise or jitter sources. A widely used TRNG is a metastable latch [1], [2] which randomly outputs '0/1' based on thermal noise. However, a metastable latch is very sensitive to offset and PVT variations, and requires careful background calibration to remove bias which degrades randomness.…”

Section: Introductionmentioning

confidence: 99%

33-200Mbps, 3pJ/Bit True Random Number Generator Based on CT Delta-Sigma Modulator

Chandrasekaran

Jayaraj

Ramesh

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This work presents a true random number generator (TRNG) that uses noise and jitter in a continuous-time, deltasigma modulator (CTDSM) as entropy source. A multi-bit nonreturn-to-zero (NRZ) feedback digital-to-analog converter (DAC) ensures that input swing seen by the front-end integrators is small and dominated by CTDSM noise and jitter, thus allowing the proposed circuit to simultaneously operate as both CTDSM and TRNG which is a key differentiation of this work compared to state-of-the-art TRNGs. Voltage controlled ring oscillators are used to implement integrators in the proposed CTDSM. Fabricated in 65nm CMOS, the TRNG has an energy efficiency of 3pJ/bit at throughput of 33Mbps and 3.5pJ/bit at 200Mbps, and passes all NIST tests with a minimum pass rate> 0.96. The measured minimum entropy of the TRNG bits is > 0.9995 across multiple chips and voltage/temperature corners without any calibration.

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“…thermal noise) to continuously generate unpredictable random numbers. Those aforementioned CMOS circuit structures can also be used to implement TRNG as long as the circuit has negligible process deviation, and its behavior is dominated by thermal noise [7][8][9][10][11]. Many security schemes require PUF and TRNG cooperating to provide very high-level security.…”

Section: Introductionmentioning

confidence: 99%

A Unified Memory and Hardware Security Module Based on the Adjustable Switching Window of Resistive Memory

Lin

Gao

Pang

et al. 2020

IEEE J. Electron Devices Soc.

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Physically unclonable function (PUF) and true random number generator (TRNG) are critical primitives to provide lightweight hardware protection. As area is tightly restricted in IoT applications, merging PUF and TRNG is a novel trend to achieve higher area efficiency. In this work, a novel tri-functional module is proposed and experimental demonstrated using RRAM for the first time. A two-phase forming process is designed to generate and store PUF ID utilizing the impact of different forming conditions on the switching window. As PUF ID is stored by the switching window, instead of a fixed resistance, PUF cells can be written to low resistance state and high resistance state as usual, and can be used as memory and TRNG. The inter-Hamming distance of the generated PUF IDs approaches 0.5, and with the majority voting readout strategy, low BER can be achieved in a wide range of temperatures from-40 o C to 125 o C. TRNG produces the true random numbers based on the parity of the number of pulses consumed in a write-zero process. The generated random numbers are uniform and uncorrelated after XORed, and the statistical randomness is verified by NIST SP800-22 tests.

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An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS

Cited by 29 publications

References 2 publications

Random-telegraph-noise-enabled true random number generator for hardware security

Random-telegraph-noise-enabled true random number generator for hardware security

33-200Mbps, 3pJ/Bit True Random Number Generator Based on CT Delta-Sigma Modulator

A Unified Memory and Hardware Security Module Based on the Adjustable Switching Window of Resistive Memory

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