An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity

Abstract

An all-MOS linear voltage-to-frequency converter (VFC) chip with 520 KHz/V sensitivity is presented in this paper. This circuit converts an input voltage into frequency by charging and discharging a capacitor. An all-MOS voltage window comparator (VWC) with reduced propagation delay is designed to improve the linearity of traditional VFCs. The propagation delay of the VWC is discussed to resolve the tradeoff between bandwidth and linearity of VFC. The proposed VFC is verified on silicon using TSMC (Taiwan Semiconductor Manufacturing Company) 1P5M 0.25 m process. The measurement results show that the linearity error is less than 1%, and the sensitivity is 520 KHz/V at the input voltage range from 0.1 to 0.8 V.

A low-power low-voltage CMOS Resistance-to-Period Converter

“…In contrast, all implementations found by the authors in literature use two comparators to generate the signal to control the charge/discharge process [4], [5], [10] (or a comparator and an amplifying stage to set the threshold voltage [6]). There are also some configurations which alternatively tum on and off the two comparators to reduce power consumption, but at the cost of complexity [11].…”

“…5 shows the proposed Current-to-Period Converter. It is based on the configuration proposed in [10], but some simple modifications make it a much more compact circuit, not the least because of the need only for one comparator.…”