14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011 Help me understand this report
An analog perspective on device reliability in 32nm high-κ metal gate technology
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Cited by 4 publications
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“…For example, in [Kri03] an optimum operating voltage to balance NBTI degradation against transistor voltage headroom is presented. A number of passive techniques, like burn-in and calibration, are used in [Cho11a,Cho11b] to compensate the aging-induced offset in different structures. Body biasing and…”
Section: Degradation Mitigation Examplesmentioning
confidence: 99%
“…For example, in [Kri03] an optimum operating voltage to balance NBTI degradation against transistor voltage headroom is presented. A number of passive techniques, like burn-in and calibration, are used in [Cho11a,Cho11b] to compensate the aging-induced offset in different structures. Body biasing and…”
Section: Degradation Mitigation Examplesmentioning
confidence: 99%
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