An analogue module generator for mixed analogue/digital asic design

Abstract

SUMMARYThis paper discusses the realization of an analogue module generator that forms part of a mixed analogue/digital design environment. It is able to design analogue functional modules such as like amplifiers, filters, etc., either in an automatic or in an interactive session, starting from performance specifications over topology selection, parameter optimization and simulation/verification down to lay-out. The analogue module generator is integrated in a commercial EDA framework. Practical design results show the capabilities and efficiency of the system.

Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

“…Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. Lampaert et al developed a performance driven analog layout tool LAYLA [13,14]. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities.…”

Computer-aided design of analog and mixed-signal integrated circuits

“…Also, this step was automated using constraint programming techniques in the DONALD tool [80]. Together with a separate topology-selection tool based on boundary checking and interval analysis [64] and a performance-driven layout generation tool [81], all these tools are now integrated into the AMGIE analog circuit synthesis system [82] that covers the complete design flow from specifications over topology selection and circuit sizing down to layout generation and automatic verification. An example of a circuit that has been synthesized with this AMGIE system is the particle/radiation detector front end of Fig.…”

Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points

“…Sizing of nominal circuits was considered in [5]- [6], £ Faculty of Electrical Engineering, University of Ljubljana, Tržaška cesta 25, 1001 Ljubljana, Slovenia e-mails: janez.puhan, arpad.buermen, tadej.tuma @fe.uni-lj.si sizing problems accounting for parameter tolerances (parameter centering) were addressed in [7]- [9], and worst-case optimization in [10]- [12]. Various optimization tools were developed, like equation based GPCAD [13], which uses geometric programming formulation of an optimization problem [14] on predefined posynomial equations, AMG [15], utilising a symbolic simulator [16] to obtain circuit equations, and the simulation based ASTRX/OBLX [17]. Recently numerous papers (e.g.…”

“…[13], [15], [17], are not integrated into commercial simulators and therefore offer only very limited capabilities), the mathematical formulation of the cost function, which would yield acceptable solutions, is rather complicated and demands an experienced user (optimization algorithms can get trapped in senseless regions of parameter space, resulting in degenerated solutions; searching for the minimum of the cost function can also result in circuits highly sensitive to manufacturing process and operating condition variations [21]; a possible solution is the use of implicit constraints [14], [20], [23]), and the results of the optimization run are not to be unlimitedly trusted (in many cases the minimum found is not the global one, even if a global optimization method was used). This paper focuses on the last of these three drawbacks.…”