An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors

Abstract

Abstract. This paper presents a survey of architectural features among four generations of Intel server processors (Sandy Bridge, Ivy Bridge, Haswell, and Broadwell) with a focus on performance with floating point workloads. Starting on the core level and going down the memory hierarchy we cover instruction throughput for floating-point instructions, L1 cache, address generation capabilities, core clock speed and its limitations, L2 and L3 cache bandwidth and latency, the impact of Cluster on Die (CoD) and cache snoop modes, and the Uncore clock speed. Using microbenchmarks we study the influence of these factors on code performance. This insight can then serve as input for analytic performance models. We show that the energy efficiency of the LINPACK and HPCG benchmarks can be improved considerably by tuning the Uncore clock speed without sacrificing performance, and that the Graph500 benchmark performance may profit from a suitable choice of cache snoop mode settings.

A performance analysis of the first generation of HPC‐optimized Arm processors

“…Triad kernel from the STREAM benchmark was run in a tight loop on each core simultaneously, with problem sizes selected to ensure residency ## https://ark.intel.com/ This portable methodology was previously shown to attain the same performance as handwritten benchmarks, which only work on their target architectures. 18 We evaluated three different compiler families for ThunderX2 in this study: GCC 7 and 8, the LLVM-based Arm HPC Compiler 18.2 and 18.3, and Cray's CCE 8.6 and 8.7. We believe this is the first study to date that has compared all three of these compilers targeting Arm.…”

On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors

“…It is well known that manufacturing variations cause significant fluctuation across chips of the same type in terms of power dissipation [7,6]. This poses problems, e.g., when power capping is enforced because power variations then translate into performance variations [7], but it can also be leveraged for saving energy by intelligent scheduling [12].…”

“…In summary, our power model yields meaningful estimates of high quality with an error below 1% for relevant operating points (i.e., away from saturation and using more than a single core). In contrast to the work in [6], where the power/performance behavior was only observed empirically, we have presented an analytic model based on simplifying assumptions that can accurately describe the observed behavior. Fig.…”

Benchmarking the first generation of production quality Arm‐based supercomputers

“…The bandwidth is then modeled using the array size, number of iterations, and the time for the benchmark to run. This portable methodology was previously shown to attain the same performance as handwritten benchmarks, which only work on their target architectures …”