2010
DOI: 10.1007/978-3-642-11389-5_6
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An Analysis of Secure Processor Architectures

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Cited by 7 publications
(9 citation statements)
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“…Software schemes [3,13,27,45,52,57] to improve security typically have unacceptably high performance overheads. Hardware schemes [11,23,28,31,32,36,37,47] are slow to react to new attacks, and can be rendered ineffective if limitations in their fixed functionality can be exploited. We want to provide a system that can avoid the shortcomings of each.…”
Section: Requirementsmentioning
confidence: 99%
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“…Software schemes [3,13,27,45,52,57] to improve security typically have unacceptably high performance overheads. Hardware schemes [11,23,28,31,32,36,37,47] are slow to react to new attacks, and can be rendered ineffective if limitations in their fixed functionality can be exploited. We want to provide a system that can avoid the shortcomings of each.…”
Section: Requirementsmentioning
confidence: 99%
“…These are particularly amenable to use of decoupled hardware that is allowed to observe the execution stream [51]. Other policies exist for providing security guarantees [23], which may also be offloaded to similar hardware, but these are beyond the scope of this paper.…”
Section: Security Detectionmentioning
confidence: 99%
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“…Secure Processors -In secure processor architectures (Lie et al, 2000;Suh et al, 2003b;Chhabra et al, 2010), data is kept in the main RAM memory in encrypted form: it is decrypted only within the secure processor when needed, then it is re-encrypted when it is written back to memory. Therefore, a physical attack aiming at spying on the traffic on the bus would only manage to see encrypted data.…”
Section: Related Workmentioning
confidence: 99%
“…Assuming a strong cipher such as AES-128 (AES, 2001), implemented in CBC mode, and a 32-bit data bus used to transfer a 64-byte data block, the overall encryption and decryption operation delays have been measured to be 97 and 141 CPU cycles, respectively (Szefer et al, 2011b). Therefore, given the above assumptions, the average number of cache misses CM, the CPU clock frequency CPU f req and the average execution time time AV , then the percentage encryption overhead of the XOM-type architectures (Lie et al, 2000;Chhabra et al, 2010), can be roughly estimated as:…”
Section: Validationmentioning
confidence: 99%