An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance

Bhowmick, Brinda; Baishya, Srimanta

doi:10.5121/vlsic.2012.3101

Cited by 2 publications

(2 citation statements)

References 17 publications

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“…To replace conventional MOSFET, new device structures are being investigated which must be compatible to CMOS circuit architecture and technology. Due to their low sub threshold swing (SS<60mv/dec), less susceptibility to short channel effects (SCEs), very low leakage current, Tunnel Field Effect Transistor (TFET) has been considered as an alternative for low power CMOS applications [4][5][6][7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Impact of Parameter Variations and Optimization on DG-PNIN Tunnel FET

Jhalani¹,

Pattanaik²

2014

VLSICS

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The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive devices for low power applications because of their low off-current and potential for smaller sub threshold slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized as performance boosters to give better current characteristics parameters. After optimization with all these performance boosters, the device has shown improved performance with increased on-current and reduced threshold voltage and the I on /I off ratio is > 10 6 .

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Section: Introductionmentioning

confidence: 99%

Impact of Parameter Variations and Optimization on DG-PNIN Tunnel FET

Jhalani¹,

Pattanaik²

2014

VLSICS

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“…However ON current of the TFET is still not adequate to compete with the MOSFET. Only few methods such as gate-drain under lap [6], heterogeneous gate (HG) dielectric (with high-k material at the source side and low-k at the drain end) [7], [8], using a spacer to separate gate and drain [9], and lower drain doping [10] are proposed to reduce the ambipolarity of the device. In this work, to enhance the ON current and reduce the ambipolarity, symmetric halo-doped DG-TFET has been proposed.…”

mentioning

confidence: 99%

Analytical Model of Symmetric Halo Doped DG - Tunnel FET

Nagarajan¹,

Korah²,

Mohankumar³

et al. 2015

JESTR

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Two-dimensional analytical model of symmetric halo doped double gate tunnel field effect transistor has been presented in this work. This model is developed based on the 2-D Poisson's equation. Some important parameters such that surface potential, vertical and lateral electric field, electric field intensity and band energy have been modelled. The doping concentration and length of halo regions are varied and dependency of various parameters is studied. The halo doping is imparted to improve the ON current and to reduce the intrinsic ambipolarity of the device. Hence we can achieve improved ION/IOFF ratio. The scaling property of halo doped structure is analyzed with various dielectric constants.

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An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance

Abstract: ABSTRACT

Cited by 2 publications

References 17 publications

Impact of Parameter Variations and Optimization on DG-PNIN Tunnel FET

Impact of Parameter Variations and Optimization on DG-PNIN Tunnel FET

Analytical Model of Symmetric Halo Doped DG - Tunnel FET

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