An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis

Davila-Raigoza, Angelica Maria; Tejero, Rubén Gran; Villarroya-Gaudó, María; Gracia, Darío Suárez

doi:10.1109/fccm48280.2020.00049

Cited by 6 publications

(4 citation statements)

References 3 publications

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“…The lack of equivalent pragmas for streaming communications in Intel API and the pass-by-pointer as parameters can result in kernels with poor performance, constraining the II up to 114 cycles, because the HLS tool generates a single Avalon Memory-Mapped (MM) Master interface with a single arbiter for all variables [26,27].…”

Section: Edgesmentioning

confidence: 99%

A Cross-Platform OpenVX Library for FPGA Accelerators

Davila-Raigoza

Tejero

Villarroya-Gaudó

et al. 2021

2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

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FPGAs are an excellent platform to implement computer vision applications, since these applications tend to offer a high level of parallelism with many data-independent operations. However, the freedom in the solution design space of FPGAs represents a problem because each solution must be individually designed, verified, and tuned. The emergence of High Level Synthesis (HLS) helps solving this problem and has allowed the implementation of open programming standards as OpenVX for computer vision applications on FPGAs, such as the HiFlipVX library developed exclusively for Xilinx devices. Although with the HiFlipVX library, designers can develop solutions efficiently on Xilinx, they do not have an approach to port and run their code on FPGAs from other manufacturers.This work extends the HiFlipVX capabilities in two significant ways: supporting Intel FPGA devices and enabling execution on discrete FPGA accelerators. To provide both without affecting user-facing code, the new carried out implementation combines two HLS programming models: C++, using Intel's system of tasks, and OpenCL, which provides the CPU interoperability. Comparing with pure OpenCL implementations, this work reduces kernel dispatch resources, saving up to 24% of ALUT resources for each kernel in a graph, and improves performance 2.6 × and energy consumption 1.6 × on average for a set of representative applications, compared with state-of-the-art frameworks.

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Section: Edgesmentioning

confidence: 99%

A Cross-Platform OpenVX Library for FPGA Accelerators

Davila-Raigoza

Tejero

Villarroya-Gaudó

et al. 2021

2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

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“…El modelo propuesto se basa en el análisis de los bloques funcionales que forman parte del GMI junto con las propiedades de las propias memorias y algunos parámetros del kernel. [6].…”

Section: Estimación Del Tiempo De Ejecución Mediante Modelado Analíticounclassified

“…Figura 1. Tiempo Medido y estimado para 16 aplicaciones limitadas por memoria usando un modelo para FPGAs basado en memoria[6] para DDR4 1866 y HBM…”

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Avances en la síntesis de alto nivel para la generación de hardware en FPGA: Modelos y programabilidad

Guzmán

Tejero²,

Gaudó³

et al. 2020

Jorn. jovenes investig. I3A

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Mejorar el rendimiento en sistemas de cómputo ha impulsado el uso de aceleradores como FPGAs. Este trabajo presenta 2 propuestas que aúnan su programabilidad y rendimiento utilizando síntesis de alto nivel, HLS, con FPGAs: 1) A través del análisis y modelado de las unidades funcionales generadas por los compiladores, con énfasis en la memoria y 2) Implementando frameworks que permitan el uso eficiente de los recursos de las FPGA en dominios específicos como la visión por computador.

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“…The compiler implements the LSU that best matches the kernel memory access pattern. However, the programmer needs to help the Altera Offline Compiler (AOC) in the code writing to choose adequate LSU as discussed in [25]. FPGAs DRAM bandwidths are typically insufficient to meet memorybound applications.…”

Section: Introductionmentioning

confidence: 99%