International Journal of Electronics

2018

DOI: 10.1080/00207217.2018.1426120

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An analytical model with flexible accuracy for deep submicron DCVSL cells

Sepideh Valiollahi

¹

,

Gholamreza Ardeshir

²

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The Proposed Voltage To Delay Conversion Methods5

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“…Furthermore, the reduction rate of the logarithm is higher than that of the exponential term in the decimator. Because, according to Valiollahi and Ardeshir, n p − m p is close to 1. Therefore, the discharging propagation delay ( τ pHL ) decreases as the input voltage ( V in ) increases.…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 86%

“…In this work, just two simplifying assumptions are applied. First, we suppose input pulses reach their final values before charging/discharging begins, so the miller capacitances between input and outputs are ignored . Second, the operating modes of transistors, used for extracting I‐V models are considered the modes; transistors remain in for the most part of the charging/discharging time.…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 99%

“…For the most part of discharging, P2 is linear mode and N2 is in saturation . As the charging process will not begin until V oHL reaches V DD min − V in − ∣ V tp ∣, V oLH is considered 0.…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 99%

“…As the charging process will not begin until V oHL reaches V DD min − V in − ∣ V tp ∣, V oLH is considered 0. Therefore, according to Equation , by applying nth‐power law I‐V model, we have

\begin{matrix} lefttrue \\ \frac{{dV}_{oHL}}{italicdt} = \frac{I_{p 2} - I_{n 2}}{C_{L}}, V_{italicoLH} (t = 0) = V_{DD max} - V_{italicin} . \\ I_{n_{2}} = I_{Dsatn 2} (1 + λ_{n} V_{DS 2}) = \frac{W_{en}}{L_{en}} B_{n} μ_{n} {((), V_{italicGS 2} - V_{tn})}^{n_{n}} (1 + λ_{n} V_{DS 2}) = \frac{W_{en}}{L_{en}} B_{n} μ_{n} {((), V_{DD} - V_{tn})}^{n_{n}} (1 + λ_{n} V_{italicoHL}), \\ I_{p_{2}} = I_{Dsatp 2} (\frac{2 V_{SD 2}}{V_{italicSDsatp 2}} - \frac{V_{italicSD 2}^{2}}{V_{SDsatp}^{2}}) (1 + λ_{p} V_{SD 2}) \approx I_{Dsatp 2} (\frac{2 V_{italicSD 2}}{V_{SDsatp 2}}) \\ = \frac{W_{ep}}{L_{ep}} B_{p} μ_{p <...>} \end{matrix}

…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 99%

“…The parameters are as explained in Valiollahi and Ardeshir . Obtaining V oHL , τ pHL is easily found by the following equation:

\begin{matrix} lefttrue \\ {(|, τ_{pHL} = t)}_{V_{italicoHL} = ((V_{DD max} - V_{italicin}) / 2)} - \frac{T_{r}}{2} \\ \to τ_{italicpHL} = \frac{A_{3} Ln (\frac{1 + λ_{n} ((), V_{italicDD max} - V_{in})}{1 + λ_{n} ((), V_{italicDD max} - V_{in}) - ((), 1 / 2) ((), V_{italicDD max} - V_{in}) ((), ((), A_{2} / A_{1}) {(V_{DD max} - V_{italicin} -| V_{tp})}^{n_{p} - m_{p}} + λ_{n})})}{A_{2} {(()||, V_{italicDD max} - V_{in} -, V_{italictp})}^{n_{p} - m_{p}} + λ_{n} A_{1}} . \end{matrix}

…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 99%

See 4 more Smart Citations

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

¹

,

²

2019

Circuit Theory & Apps

Self Cite

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Summary Translating the analog input voltage to delay of delay cells is a necessity for realizing digital time‐based quantization. Usually, this conversion is done through additional elements, imposing extra power and area. This paper proposes a voltage to delay conversion method for cross‐coupled differential cascode voltage switch logic (DCVSL) cells, without adding any extra elements to their basic structures. Cross‐coupled delay cells are superior to conventional CMOS inverters in terms of lower power consumption, propagation delay, and area. However, controlling their delay is a demanding task due to their asynchronous charging and discharging. The key features of the proposed method are (a) controlling the delay of DCVSL cells just by see‐saw changing of PMOS transistors source voltages; (b) reducing the propagation delays of DCVSL cells by simultaneously accelerating the charging and discharging processes; (c) reducing the power consumption by decreasing both the switching time and short‐circuit current; (d) employing the proposed voltage to delay conversion method to develop a low power, small area, all‐digital time‐based analog to digital converter (ADC). The proposed 4‐bit ADC, implemented in TSMC 65‐nm CMOS technology, consumes 0.37 mW at conversion speed of 2 GHz with SNDR 20.9 dB and SFDR 30.2 dB, and occupies an active area of 0.0029 mm2.

“…Furthermore, the reduction rate of the logarithm is higher than that of the exponential term in the decimator. Because, according to Valiollahi and Ardeshir, n p − m p is close to 1. Therefore, the discharging propagation delay ( τ pHL ) decreases as the input voltage ( V in ) increases.…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 86%

“…In this work, just two simplifying assumptions are applied. First, we suppose input pulses reach their final values before charging/discharging begins, so the miller capacitances between input and outputs are ignored . Second, the operating modes of transistors, used for extracting I‐V models are considered the modes; transistors remain in for the most part of the charging/discharging time.…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 99%

“…For the most part of discharging, P2 is linear mode and N2 is in saturation . As the charging process will not begin until V oHL reaches V DD min − V in − ∣ V tp ∣, V oLH is considered 0.…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 99%

“…As the charging process will not begin until V oHL reaches V DD min − V in − ∣ V tp ∣, V oLH is considered 0. Therefore, according to Equation , by applying nth‐power law I‐V model, we have

\begin{matrix} lefttrue \\ \frac{{dV}_{oHL}}{italicdt} = \frac{I_{p 2} - I_{n 2}}{C_{L}}, V_{italicoLH} (t = 0) = V_{DD max} - V_{italicin} . \\ I_{n_{2}} = I_{Dsatn 2} (1 + λ_{n} V_{DS 2}) = \frac{W_{en}}{L_{en}} B_{n} μ_{n} {((), V_{italicGS 2} - V_{tn})}^{n_{n}} (1 + λ_{n} V_{DS 2}) = \frac{W_{en}}{L_{en}} B_{n} μ_{n} {((), V_{DD} - V_{tn})}^{n_{n}} (1 + λ_{n} V_{italicoHL}), \\ I_{p_{2}} = I_{Dsatp 2} (\frac{2 V_{SD 2}}{V_{italicSDsatp 2}} - \frac{V_{italicSD 2}^{2}}{V_{SDsatp}^{2}}) (1 + λ_{p} V_{SD 2}) \approx I_{Dsatp 2} (\frac{2 V_{italicSD 2}}{V_{SDsatp 2}}) \\ = \frac{W_{ep}}{L_{ep}} B_{p} μ_{p <...>} \end{matrix}

…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 99%

“…The parameters are as explained in Valiollahi and Ardeshir . Obtaining V oHL , τ pHL is easily found by the following equation:

\begin{matrix} lefttrue \\ {(|, τ_{pHL} = t)}_{V_{italicoHL} = ((V_{DD max} - V_{italicin}) / 2)} - \frac{T_{r}}{2} \\ \to τ_{italicpHL} = \frac{A_{3} Ln (\frac{1 + λ_{n} ((), V_{italicDD max} - V_{in})}{1 + λ_{n} ((), V_{italicDD max} - V_{in}) - ((), 1 / 2) ((), V_{italicDD max} - V_{in}) ((), ((), A_{2} / A_{1}) {(V_{DD max} - V_{italicin} -| V_{tp})}^{n_{p} - m_{p}} + λ_{n})})}{A_{2} {(()||, V_{italicDD max} - V_{in} -, V_{italictp})}^{n_{p} - m_{p}} + λ_{n} A_{1}} . \end{matrix}

…”

Section: The Proposed Voltage To Delay Conversion Methodsmentioning

confidence: 99%

See 3 more Smart Citations

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

¹

,

²

2019

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

Summary Translating the analog input voltage to delay of delay cells is a necessity for realizing digital time‐based quantization. Usually, this conversion is done through additional elements, imposing extra power and area. This paper proposes a voltage to delay conversion method for cross‐coupled differential cascode voltage switch logic (DCVSL) cells, without adding any extra elements to their basic structures. Cross‐coupled delay cells are superior to conventional CMOS inverters in terms of lower power consumption, propagation delay, and area. However, controlling their delay is a demanding task due to their asynchronous charging and discharging. The key features of the proposed method are (a) controlling the delay of DCVSL cells just by see‐saw changing of PMOS transistors source voltages; (b) reducing the propagation delays of DCVSL cells by simultaneously accelerating the charging and discharging processes; (c) reducing the power consumption by decreasing both the switching time and short‐circuit current; (d) employing the proposed voltage to delay conversion method to develop a low power, small area, all‐digital time‐based analog to digital converter (ADC). The proposed 4‐bit ADC, implemented in TSMC 65‐nm CMOS technology, consumes 0.37 mW at conversion speed of 2 GHz with SNDR 20.9 dB and SFDR 30.2 dB, and occupies an active area of 0.0029 mm2.

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