An Approach for Development of RISC- V Based Transport Layer Controller

Suvorova, Elena

doi:10.1109/weconf51603.2021.9470646

Cited by 2 publications

(1 citation statement)

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“…Moreover, an approach to developing a dynamically reconfigurable transport layer controller architecture in ASIC was presented by Suvorova [12]. These designs were based on dynamically reconfigurable automata and finite state machine [13], [14] with DataPath [15], [16]. For more efficiency, Suvorova [17] proposed an approach to developing a dynamically reconfigurable transport layer controller based on a processor core with reduced instruction set computer V (RISC-V) architecture.…”

Section: Introductionmentioning

confidence: 99%

Architecture Design of Protocol Controller Based on Traffic-Driven Software Defined Interconnection

Li,

Shen,

Lyu

et al. 2024

Chinese J. Elect.

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To solve the problems of redundant logic resources and poor scalability in protocol controller circuits among communication networks, we propose a traffic-driven software defined interconnection (TSDI) mechanism. The unified software defined interconnection interface standards and the normalized interconnection topology are designed to implement the architecture of TSDI-based protocol controller. The key indicators of power, performance and area (PPA) can be realized while resolving the flexible interconnection of the controller. We designed a TSDI-based RapidIO controller as an example. Compared to traditional designs, the design could achieve more protocol scalability, and RapidIO protocol standards of Gen4 could be supported directly. The key PPA indicators, such as a lower delay of 56.1 ns and more than twice throughput of 98.1 Gbps, were achieved at the cost of a 23.4% area increase.

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