2013
DOI: 10.1007/s11334-013-0220-0
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An approach to instruction set compiled simulator development based on a target processor C compiler back-end design

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Cited by 2 publications
(2 citation statements)
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“…The main goal of the paper is to add the capability of automatic parallelization of existing sequential C code to C compiler, which has been previously developed by our group [6][7][8]. This C compiler is targeting modern digital signal processors (DSP), including Cirrus Logic Coyote 32 architecture, which is also our target architecture (TA).Significant part of this C compiler is reused.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…The main goal of the paper is to add the capability of automatic parallelization of existing sequential C code to C compiler, which has been previously developed by our group [6][7][8]. This C compiler is targeting modern digital signal processors (DSP), including Cirrus Logic Coyote 32 architecture, which is also our target architecture (TA).Significant part of this C compiler is reused.…”
Section: Introductionmentioning
confidence: 99%
“…Existing global scheduler [7] could be reused for scheduling instructions of parallel program to each core, as well. Besides, the C compiler could be extended with already developed instruction set compiled simulator for Coyote DSP [8], which would certainly have to be extended for use with modified compiler, i.e. for simulation of parallel program execution.…”
Section: Introductionmentioning
confidence: 99%