An approach to parallelizing non-uniform loops with the Omega calculator

Journal of Parallel and Distributed Computing

2011

Cataloged from PDF version of article.Embedded applications are becoming increasingly complex and processing ever-increasing datasets. In\ud the context of data-intensive embedded applications, there have been two complementary approaches to\ud enhancing application behavior, namely, data locality optimizations and improving loop-level parallelism.\ud Data locality needs to be enhanced to maximize the number of data accesses satisfied from the higher\ud levels of the memory hierarchy. On the other hand, compiler-based code parallelization schemes require\ud a fresh look for chip multiprocessors as interprocessor communication is much cheaper than off-chip\ud memory accesses. Therefore, a compiler needs to minimize the number of off-chip memory accesses. This\ud can be achieved by considering multiple loop nests simultaneously. Although compilers address these two\ud problems, there is an inherent difficulty in optimizing both data locality and parallelism simultaneously.\ud Therefore, an integrated approach that combines these two can generate much better results than each\ud individual approach. Based on these observations, this paper proposes a constraint network (CN)-based\ud formulation for data locality optimization and code parallelization. The paper also presents experimental\ud evidence, demonstrating the success of the proposed approach, and compares our results with those\ud obtained through previously proposed approaches. The experiments from our implementation indicate\ud that the proposed approach is very effective in enhancing data locality and parallelization.\ud © 2010 Elsevier Inc. All rights reserved

Section: Discussion Of Related Workmentioning

confidence: 99%

Data locality and parallelism optimization using a constraint-based approach

Journal of Parallel and Distributed Computing

2011

“…Yu and D'Hollander [23] construct an iteration space dependency graph to visualize a 3D iteration space. Beletskyy et al [6] adopt a hyperplane-based representation to apply on transformation matrices with both uniform and non-uniform dependences. Lim et al [18] employ affine partitioning to maximize parallelism with minimum communication overhead.…”

Section: Related Workmentioning

confidence: 99%

Code Scheduling for Optimizing Parallelism and Data Locality

Yemliha

Kandemir

Euro-Par 2010 - Parallel Processing

et al. 2010

As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. Unfortunately, most of the published work in the literature focuses only on one of these problems, and this can prevent one from achieving the best possible performance. The main goal of this paper is to propose and evaluate a compiler-directed code parallelization scheme, which considers both parallelism and data locality at the same time. Our compiler captures the inherent parallelism and data reuse in the application code being analyzed using a novel representation called the locality-parallelism graph (LPG). Our partitioning/scheduling algorithm assigns the nodes of this graph to the processors in the architecture and schedules them for execution. We implemented this algorithm and evaluated its effectiveness using a set of benchmark codes. The results collected so far indicate that our approach improves overall execution latency significantly. In this paper, we also introduce an ILP (Integer Linear Programming) based formulation of the problem, and implement the schedule obtained by the ILP solver. The results indicate that our approach gets within 4% of the ILP solution.1 In some cases, increasing the number of processors used beyond a certain point can degrade performance due to increased inter-processor communication.

“…Similarly, the access pattern for the same array when the j loop is parallelized (instead of i) can be captured as [block(4), * ]. If, on the other hand, for a three-dimensional array in a different example, the first, second, and third dimensions are distributed over 3, 2, and 6 processors, respectively, the resulting data access pattern can be specified as [block (3), block(2), block (6)]. Capturing access patterns on different arrays is important because if two different loops, say i and j, of two different nests have the same access patterns on the same set of arrays, these two loops are good candidates for parallelization.…”

Section: Preprocessingmentioning

confidence: 99%

“…An iteration space dependency graph is constructed to show the data dependencies and to indicate the maximal parallelism of nested loops. Beletskyy et al [3] propose an approach to parallelize loops with nonuniform dependences. By adopting a hyperplane based representation, they present how transformation matrices can be found and applied to loops with both uniform and non-uniform dependences.…”

Section: Related Workmentioning

confidence: 99%

Optimizing code parallelization through a constraint network based approach

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

Chen

Kandemir

2006

Increasing employment of chip multiprocessors in embedded computing platforms requires a fresh look at conventional code parallelization schemes. In particular, any compiler-based parallelization scheme for chip multiprocessors should account for the fact that interprocessor communication is cheaper than off-chip memory accesses in these architectures. Based on this observation, this paper proposes a constraint network based approach to code parallelization for chip multiprocessors. Constraint networks have proven to be a useful mechanism for modeling and solving computationally intensive tasks in artificial intelligence. They operate by expressing a problem as a set of variables, variable domains and constraints and define a search procedure that tries to satisfy the constraints (an acceptable subset of them) by assigning values to variables from their specified domains. This paper demonstrates that it is possible to use a constraint network based formulation for the problem of code parallelization for chip multiprocessors. Our experimental evaluation shows that not only a constraint network based approach is feasible for our problem but also highly desirable since it outperforms all other parallelization schemes tested in our experiments.