An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis

Wang, Xiaoying; Hedrich, Lars

doi:10.1145/1118299.1118463

Cited by 11 publications

(5 citation statements)

References 12 publications

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“…The first ideas towards the current methodology were published in [WH06,MMH11c,MMH11d], which are used as a blueprint for the core synthesis algorithm, although all rules were reformulated, some of the basic concepts still exist inside the presented work.…”

Section: Contributions and Publicationsmentioning

confidence: 99%

“…A widespread solution for the lack of trust is the concept of basic blocks. First introduced by [DCR05] and Wang et al [WH06] the concept has been widely used (see [MPSG09,DV08]) to overcome the trust drawbacks and to reduce the computational complexity of analog circuit synthesis.…”

Section: State-of-the-art In Analog Synthesismentioning

confidence: 99%

“…The concept of constructive rules originates in the first publications of this methodology in [WH06,MMH11c]. These were fundamentally reformulated towards genericity during the migration to the graph based approach first presented in [MMH11b,MMH11a] and are in its current evolution fully independent from specific basic blocks, thus allow the constructive synthesis to use any basic block provided by the user as published in [MH15].…”

Section: Constructive Rulesmentioning

confidence: 99%

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FEATS: Framework for Explorative Analog Topology Synthesis

Meißner

Hedrich

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The presented work inside this thesis aims to raise the degree of automation in analog circuit design. Therefore, a framework was developed to provide the necessary mechanisms in order to carry out a fully automated analog circuit synthesis, i.e., the construction of an analog circuit fulfilling all previously defined (electrical) specifications.Nowadays, analog circuit design in general is a very time consuming process compared to a digital design flow. Due to its discrete nature, the digital design process is highly automated and thus very efficient compared to analog circuit design. In modern Very-Large-Scale integration (VLSI) circuits the analog parts are mostly just a small portion of the overall chip area. Although this small portion is known to consume a major part of the needed workforce. Paired with product cycles which constantly get shorter, the time needed to develop the analog parts of an integrated circuit (IC) becomes a determinant factor. Apart from this, the ongoing progress in semiconductor processing technologies promises more speed with less power consumption on smaller areas, forcing the IC developers to keep track with the technology nodes in order to maintain competitiveness. Analog circuitry exhibits the inherent property of being hard to reuse, as porting from one technology node to another imposes critical changes for operating conditions (e.g., supply voltage) -mostly leading to a full redesign for most of the analog modules. This productivity gap between digital and analog design resembles the primary motivation for this thesis.Due to the availability of commercial sizing tools, this work deliberately focuses on the construction of circuit topologies in distinction to parameter synthesis, which can be obtained with a dedicated sizing tool. The focus on circuit construction allows the development of a framework which allows a full design space exploration. This thesis describes the needed concepts and methods to realize a deterministic, explorative analog synthesis framework. Despite this, a reference implementation is presented, which demonstrates the applicability in current analog design flows. circuit (c) a circuit representing a physical realization circuits (C) an unordered set of circuits design space (DS) design space seen as crossproduct of P S and ST S devices (M ) an unordered set of devices equivalence class (eqcls) an unordered set of objects sharing the combination set of invariant properties equivalence classes (EQCLS(c)) set of equivalence classes associated with the circuit c graph (G) a representation of object vertices connected through edges ground (V GN D ) name of the reference net or simply ground hash (hash(x)) hash associated with object x integer (N) integer numbers invariant properties (EQP ROP S(x)) set of invariant properties associated with x invariant property (p) a property associated with a specific IV i invariants (IV) an unordered set of invariants label (L(x)) label associated with object x nets (N ) an unordered set of nets parameter space ...

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Section: Contributions and Publicationsmentioning

confidence: 99%

Section: State-of-the-art In Analog Synthesismentioning

confidence: 99%

Section: Constructive Rulesmentioning

confidence: 99%

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FEATS: Framework for Explorative Analog Topology Synthesis

Meißner

Hedrich

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…But they required substantial computational overhead and produced functionally correct but unfamiliar circuits. To alleviate this, Dastidar et al [6] and Wang et al [7] blended some design knowledge, although minimal, with the evolutionary aspects. They used a fixed set of user-defined building blocks and connectivity rules to evolve analog circuits.…”

Section: Introductionmentioning

confidence: 99%

“…They used a fixed set of user-defined building blocks and connectivity rules to evolve analog circuits. Unfortunately, the approach in [6], [7] has drawbacks, too. First, the methods fail completely in the absence of a well-defined library.…”

Section: Introductionmentioning

confidence: 99%

ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework

Das

Vemuri

2008

2008 IEEE International Symposium on Circuits and Systems

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Abstract-This paper presents ATLAS -a framework for automated analog circuit synthesis that comprises of both topology generation and subsequent circuit sizing. A hierarchically arranged building block or cell library is used in this regard. The adaptively formed library starts only with basic elements and gradually includes functionally useful and bigger blocks, pertinent to the design under consideration. The sizer is based on the simulated annealing algorithm, and HSPICE is used for performance evaluation. The tool has been used to synthesize an operational amplifier and a ring oscillator. Results show that with reasonable computational effort, designs and associated cells have evolved that are human understandable and comparable to hand-crafted designs.

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Automated topology synthesis of analog and RF integrated circuits: A survey

Sorkhabi

Zhang

2017

Integration

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An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis

Cited by 11 publications

References 12 publications

FEATS: Framework for Explorative Analog Topology Synthesis

FEATS: Framework for Explorative Analog Topology Synthesis

ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework

Automated topology synthesis of analog and RF integrated circuits: A survey

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