An Architectural Framework for Detecting Process Hangs/Crashes

Nakka, Nithin; Saggese, G.P.; Kalbarczyk, Zbigniew; Iyer, Ravishankar K.

doi:10.1007/11408901_8

Cited by 21 publications

(19 citation statements)

References 11 publications

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“…Hang detection for microprocessors has been implemented on FPGAs [20]. Nakka et al [21] separate hang detection for microprocessors into three categories. First, Instruction-Count Heartbeat (ICH) detects a hung process not executing any instructions.…”

Section: Related Researchmentioning

confidence: 99%

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Curreri

Stitt

George

2011

International Journal of Reconfigurable Computing

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Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy registertransfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

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Section: Related Researchmentioning

confidence: 99%

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Curreri

Stitt

George

2011

International Journal of Reconfigurable Computing

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“…Ragel et al proposed a basic block validation scheme in [20] by modifying the processor's microinstructions. Nakka et al proposed a processor pipeline modification framework in [12] for detecting a process crash or hang. Wang et al proposed checking the instruction counter register at the function level in [26] for detecting incorrect execution paths in programs.…”

Section: Related Workmentioning

confidence: 99%

“…Access to the instruction register (IR) is also unavailable in Xtensa LX2 and hence signature verification proposed in [11] is not possible. The microinstructions modification required for [20] and the pipeline modification required for [12] are also not possible due to the unavailability of the base processor's hardware description. The approach proposed in [26] needs various training data sets to build the instruction count values for program path patterns.…”

Section: Related Workmentioning

confidence: 99%

CUFFS: An instruction count based architectural framework for security of MPSoCs

Patel¹,

Parameswaran²,

Ragel³

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to cause software attacks, which are the most common type of attacks on embedded systems. Therefore, we propose an MPSoC architectural framework, CUFFS, for an Application Specific Instruction set Processor (ASIP) design that has a dedicated security processor called iGuard for detecting software attacks.The CUFFS framework instruments the source code in the application processors at the basic block (BB) level with special instructions that allow communication with iGuard at runtime. The framework also analyzes the code in each application processor at compile time to determine the program control flow graph and the number of instructions in each basic block, which are then stored in the hardware tables of iGuard. The iGuard uses its hardware tables to verify the applications' execution at runtime. For the first time, we propose a framework that probes the application processors to obtain their Instruction Count and employs an actively engaging security processor that can detect attacks even when an application processor does not communicate with iGuard.CUFFS relies on the exact number of instructions in the basic block to determine an attack which is superior to other time-frame based measures proposed in the literature. We present a systematic analysis on how CUFFS can thwart common software attacks. Our implementation of CUFFS on the Xtensa LX2 processor from Tensilica Inc. had a worst case runtime penalty of 44% and an area overhead of about 28%.

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“…Sometimes even the mouse cursor does not move either. "Unresponsiveness", "freeze" and "hang" have been used to describe such a phenomenon, with "hang" being the most popular [1]- [4], [6], [7], [9], [12]. Note that a single program unresponsive failure (i.e., one application failing to respond to user input) is regarded as application hang, which is not the focus in this paper.…”

Section: Introductionmentioning

confidence: 99%

“…Second, most methodologies for detecting system hang need additional assistance, provided by either new hardware modules [7], modified OS kernels [1], [5], or monitor breakpoints inserted dynamically for interested code regions [4]. Can we rely on the existing services provided by the OS to detect system hang effectively?…”

Section: Introductionmentioning

confidence: 99%