An architectural framework for supporting heterogeneous instruction-set architectures

Silberman, Gabriel M.; Ebcioğlu, Kemal

doi:10.1109/2.214441

Cited by 38 publications

(13 citation statements)

References 7 publications

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“…50 There was a desire to convert existing VAX software to the Alpha platform, without using the original source code. Another system 51 talks about emulating complex instruction set machines by using binary translation within a RISC environment.…”

Section: Binary Translationmentioning

confidence: 99%

Heterogeneous process migration: the Tui system

Smith

Hutchinson

1998

Softw: Pract. Exper.

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SUMMARYHeterogeneous process migration is a technique whereby an active process is moved from one machine to another. It must then continue normal execution and communication. The source and destination processors can have a different architecture, that is, different instruction sets and data formats. Because of this heterogeneity, the entire process memory image must be translated during the migration. Tui is a migration system that is able to translate the memory image of a program (written in ANSI-C) between four common architectures (m68000, SPARC, i486 and PowerPC). This requires detailed knowledge of all data types and variables used with the program. This is not always possible in non-type-safe (but popular) languages such as ANSI-C, Pascal and Fortran. The important features of the Tui algorithm are discussed in great detail. This includes the method by which a program's entire set of data values can be located, and eventually reconstructed on the target processor. Performance figures demonstrating the viability of using Tui to migrate real applications are given.

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Section: Binary Translationmentioning

confidence: 99%

Heterogeneous process migration: the Tui system

Smith

Hutchinson

1998

Softw: Pract. Exper.

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“…To solve the compatibility problem efficiently, there have been several proposals beyond plain or caching interprctcrs [lo]. One has been the object code translation approach (c,g, [20,21,22,23]), where a software program takes as input an executable module generated for the old machine, and profile directed feedback information from past emulations, if available. It then generates a new executable module that can run on thenew architecture (resorting to interpretation in some difficult cases), and that gives the same results that plain interpretationwould.…”

Section: Background and Motivationmentioning

confidence: 99%

Daisy

Ebcioğlu

Altman

1997

SIGARCH Comput. Archit. News

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Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impedimegt to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call DAISY (Dynamically Architected Instruction Set from Yorlrtown). DAISY is specifically intended to emulate existing architectures, so that all existing software for an old architecture (including operating system kernel code) runs without changes on the VLIW. Each time a new fragment of code is executed for the first time, the code is translated to VLIW primitives, parallelized and saved in a portion of main memory not visible to the old architecture, by a Ertual Machine Monitor (software) residing in read only memory. Subsequent executions of the same fragment do not require a translation (unless cast out). We discuss the architectural requirements for such a VLIW, to deal with issues including self-modifying code, precise exceptions, and aggressive reordering of memory references in the presence of strong MP consistency and memory mapped I/O. We have implemented the dynamic parallelization algorithms for the PowerPC architecture. The initial results show high degrees of instruction level parallelism with reasonable translation overhead and memory usage.

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“…Due to past progress in the binary translation and optimization field, the binary instructions of an ISA are by now a de facto compiler intermediate language[17,18,43] which allows access to a wide range of applications.…”

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confidence: 99%

Memory Partitioning in the Limit

Kültürsay

Ebcioğlu

Küçük

et al. 2015

Int J Parallel Prog

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The key difficulties in designing memory hierarchies for future computing systems with extreme scale parallelism include (1) overcoming the design complexity of system-wide memory coherence, (2) achieving low power, and (3) achieving fast access times within such a memory hierarchy. Towards addressing these difficulties, in this paper we propose an automatic memory partitioning method to generate a customized, application-specific, energy-efficient, low latency memory hierarchy, tailored to particular application programs. Given a software program to accelerate, our method automatically partitions the memory of the original program, creates a new customized application-specific multi-level memory hierarchy for the program, and modifies the original program to use the new memory hierarchy. This new memory hierarchy and modified program are then used as the basis to create a customized, application-specific, highly parallel hardware accelerator, which is functionally equivalent to the original, unmodified program. Using dependence analysis and fine grain valid/dirty bits, the memories in the generated hierarchy can operate in parallel with-B Emre Kültürsay 123 338 Int J Parallel Prog (2016) 44:337-380 out the need for maintaining coherence and can be independently initialized/flushed from/to their parent memories in the hierarchy, enabling a scalable memory design. The generated memories are fully compatible with the memory addressing in the original software program; this compatibility feature enables the translation of general software applications to application-specific accelerators. We also provide a compiler analysis method to perform accurate dependence analysis for memory partitioning based on symbolic execution, and a profiler-based futuristic limit study to identify the maximum gains that can be achieved by memory partitioning.

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An architectural framework for supporting heterogeneous instruction-set architectures

Cited by 38 publications

References 7 publications

Heterogeneous process migration: the Tui system

Heterogeneous process migration: the Tui system

Daisy

Memory Partitioning in the Limit

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